On Mon, 2008-08-04 at 17:40 -0600, Paul Walmsley wrote:
> Add the MT_MEMORY_STRONGLY_ORDERED memory type for ARM strongly ordered
> memory.
>
> This is used on OMAP3 for on-board SRAM. On OMAP, SRAM is used for code
> that changes the SDRAM controller's clock, temporarily blocking access to
> SDRAM. During this period, as code executes from SRAM, the ARM cache
> controller can attempt to write dirty cache lines back to SDRAM to make
> room for SRAM cache lines, causing the MPU subsystem to hang. To avoid
> this, we mark SRAM as strongly- ordered memory.
Why not use normal uncached memory? Strongly ordered is pretty
inefficient as it cannot do any reordering or write buffer merging (it's
like having a memory barrier before and after each instruction).
Speculative accesses are not allowed either. Strongly ordered memory is
not really meant for executing code from.
> + [MT_MEMORY_STRONGLY_ORDERED] = {
> + .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE |
> + PMD_SECT_UNCACHED,
You can add PMD_SECT_TEX(1) for normal uncached memory.
--
Catalin
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