Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@xxxxxxxxx>
---
arch/arm/mach-omap2/clock34xx.c | 6 +++++-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 6bb25cf..b0bc1b9 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -46,6 +46,8 @@
#define MAX_DPLL_WAIT_TRIES 1000000
+#define OFFMODE_POL (1<<3)
+
struct vdd_prcm_config *curr_vdd1_prcm_set;
struct vdd_prcm_config *curr_vdd2_prcm_set;
static struct clk *dpll1_clk, *dpll2_clk, *dpll3_clk;
@@ -684,6 +686,9 @@ int __init omap2_clk_init(void)
}
#endif
+ prm_clear_mod_reg_bits(OFFMODE_POL, OMAP3430_GR_MOD,
+ OMAP3_PRM_POLCTRL_OFFSET);
+
printk(KERN_INFO "Clocking rate (Crystal/DPLL/ARM core): "
"%ld.%01ld/%ld/%ld MHz\n",
(osc_sys_ck.rate / 1000000), (osc_sys_ck.rate / 100000) % 10,
@@ -797,7 +802,6 @@ static int omap3_select_table_rate(struct clk *clk, unsigned long rate)
return -EINVAL;
}
-
if (clk == &virt_vdd1_prcm_set) {
curr_mpu_speed = curr_vdd1_prcm_set->speed;
clk_set_rate(dpll1_clk, prcm_vdd->speed);
--
1.5.3.4
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