3430ES2+ CORE DPLL M2 divider can divide by 1 to 31, unlike ES1, which was more limited. The SRAM code currently only supports dividing by 1 or 2, but we should mask off the full range of bits to guard against the event that the previous contents of CM_CLKSEL_PLL1 included an M2 divider > 2. Signed-off-by: Paul Walmsley <paul@xxxxxxxxx> --- arch/arm/mach-omap2/sram34xx.S | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 63db781..1acdbe8 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -173,7 +173,7 @@ omap3_sdrc_dlla_status: omap3_sdrc_dlla_ctrl: .word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL) core_m2_mask_val: - .word 0xE7FFFFFF + .word 0x07FFFFFF ENTRY(omap3_sram_configure_core_dpll_sz) .word . - omap3_sram_configure_core_dpll -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
