Re: [PATCH] New DPLL clock framework.

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On Thu, 13 Mar 2008, Roman Tereshonkov wrote:

> 	These changes is the result of the discussion with Paul Walmsley.
> 	His ideas are included into this patch.
> 
> 	Remove DPLL output divider handling from DPLLs and CLKOUTX2 clocks,
> 	and place it into specific DPLL output divider clocks (e.g., dpll3_m2_clk).
> 	omap2_get_dpll_rate() now returns the correct DPLL rate, as represented
> 	by the DPLL's CLKOUT output. Also add MPU and IVA2 subsystem clocks, along
> 	with high-frequency bypass support.
> 
> 	Add support for DPLLs function in locked and bypass clock modes.
> 
> Signed-off-by: Roman Tereshonkov <roman.tereshonkov@xxxxxxxxx>

Looks good to me Roman, thanks.

Acked-by: Paul Walmsley <paul@xxxxxxxxx>

- Paul
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