From: Kevin Hilman <khilman@xxxxxxxxxx>
On OMAP2/3, the gp-timer code can be used for a 32kHz timer simply by
setting the source to be the 32k clock instead of sys_clk.
This patch uses the mach-omap2/timer-gp.c code for 32kHz timer on
OMAP2, moving the logic into mach-omap2/timer-gp.c, and not using
plat-omap/timer32k.c which, for OMAP2, is redundant with the timer-gp
code.
Also, if CONFIG_OMAP_32K_TIMER is enabled, the gptimer-based
clocksource is not used. Instead the default 32k sync counter is used
as the clocksource (see the clocksource in plat-omap/common.c.) This
is important for sleep/suspend so there is a valid counter during
sleep. Note that the suspend/sleep code needs fixing to check for
overflows of this counter.
In addition, the OMAP2/3 details are removed from timer32k.c leaving
that with only OMAP1 specifics. A follow-up patch will move it from
plat-omap common code to mach-omap1.
Signed-off-by: Kevin Hilman <khilman@xxxxxxxxxx>
Signed-off-by: Tony Lindgren <tony@xxxxxxxxxxx>
---
arch/arm/mach-omap2/Makefile | 4 +-
arch/arm/mach-omap2/timer-gp.c | 152 ++++++++++++++++++++++++++++++++++++----
arch/arm/plat-omap/Makefile | 2 +
arch/arm/plat-omap/timer32k.c | 44 +-----------
4 files changed, 141 insertions(+), 61 deletions(-)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b05b738..ac343ec 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,9 +4,7 @@
# Common support
obj-y := irq.o id.o io.o sram-fn.o memory.o prcm.o clock.o mux.o devices.o \
- serial.o gpmc.o
-
-obj-$(CONFIG_OMAP_MPU_TIMER) += timer-gp.o
+ serial.o gpmc.o timer-gp.o
# Power Management
obj-$(CONFIG_PM) += pm.o pm-domain.o sleep.o
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 3234dee..78d05f2 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -3,6 +3,11 @@
*
* OMAP2 GP timer support.
*
+ * Update to use new clocksource/clockevent layers
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@xxxxxxxxxx>
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * Original driver:
* Copyright (C) 2005 Nokia Corporation
* Author: Paul Mundt <paul.mundt@xxxxxxxxx>
* Juha Yrjölä <juha.yrjola@xxxxxxxxx>
@@ -25,24 +30,23 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/irq.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
#include <asm/mach/time.h>
#include <asm/arch/dmtimer.h>
static struct omap_dm_timer *gptimer;
-
-static inline void omap2_gp_timer_start(unsigned long load_val)
-{
- omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
- omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
- omap_dm_timer_start(gptimer);
-}
+static struct clock_event_device clockevent_gpt;
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
- omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
- timer_tick();
+ struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
+ struct clock_event_device *evt = &clockevent_gpt;
+
+ omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
+ evt->event_handler(evt);
return IRQ_HANDLED;
}
@@ -52,20 +56,138 @@ static struct irqaction omap2_gp_timer_irq = {
.handler = omap2_gp_timer_interrupt,
};
-static void __init omap2_gp_timer_init(void)
+static int omap2_gp_timer_set_next_event(unsigned long cycles,
+ struct clock_event_device *evt)
{
- u32 tick_period;
+ omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles);
+ omap_dm_timer_start(gptimer);
+
+ return 0;
+}
+
+static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+ u32 period;
+
+ omap_dm_timer_stop(gptimer);
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
+ period -= 1;
+
+ omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period);
+ omap_dm_timer_start(gptimer);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ case CLOCK_EVT_MODE_RESUME:
+ break;
+ }
+}
+
+static struct clock_event_device clockevent_gpt = {
+ .name = "gp timer",
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .shift = 32,
+ .set_next_event = omap2_gp_timer_set_next_event,
+ .set_mode = omap2_gp_timer_set_mode,
+};
+
+static void __init omap2_gp_clockevent_init(void)
+{
+ u32 tick_rate;
- omap_dm_timer_init();
gptimer = omap_dm_timer_request_specific(1);
BUG_ON(gptimer == NULL);
+#if defined(CONFIG_OMAP_32K_TIMER)
+ omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
+#else
omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK);
- tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
- tick_period -= 1;
+#endif
+ tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
+ omap2_gp_timer_irq.dev_id = (void *)gptimer;
setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
- omap2_gp_timer_start(tick_period);
+ omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
+
+ clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
+ clockevent_gpt.shift);
+ clockevent_gpt.max_delta_ns =
+ clockevent_delta2ns(0xffffffff, &clockevent_gpt);
+ clockevent_gpt.min_delta_ns =
+ clockevent_delta2ns(1, &clockevent_gpt);
+
+ clockevent_gpt.cpumask = cpumask_of_cpu(0);
+ clockevents_register_device(&clockevent_gpt);
+}
+
+#ifdef CONFIG_OMAP_32K_TIMER
+/*
+ * When 32k-timer is enabled, don't use GPTimer for clocksource
+ * instead, just leave default clocksource which uses the 32k
+ * sync counter. See clocksource setup in see plat-omap/common.c.
+ */
+
+static inline void __init omap2_gp_clocksource_init(void) {}
+#else
+/*
+ * clocksource
+ */
+static struct omap_dm_timer *gpt_clocksource;
+static cycle_t clocksource_read_cycles(void)
+{
+ return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
+}
+
+static struct clocksource clocksource_gpt = {
+ .name = "gp timer",
+ .rating = 300,
+ .read = clocksource_read_cycles,
+ .mask = CLOCKSOURCE_MASK(32),
+ .shift = 24,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+/* Setup free-running counter for clocksource */
+static void __init omap2_gp_clocksource_init(void)
+{
+ static struct omap_dm_timer *gpt;
+ u32 tick_rate, tick_period;
+ static char err1[] __initdata = KERN_ERR
+ "%s: failed to request dm-timer\n";
+ static char err2[] __initdata = KERN_ERR
+ "%s: can't register clocksource!\n";
+
+ gpt = omap_dm_timer_request();
+ if (!gpt)
+ printk(err1, clocksource_gpt.name);
+ gpt_clocksource = gpt;
+
+ omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
+ tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
+ tick_period = (tick_rate / HZ) - 1;
+
+ omap_dm_timer_set_load(gpt, 1, 0);
+ omap_dm_timer_start(gpt);
+
+ clocksource_gpt.mult =
+ clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
+ if (clocksource_register(&clocksource_gpt))
+ printk(err2, clocksource_gpt.name);
+}
+#endif
+
+static void __init omap2_gp_timer_init(void)
+{
+ omap_dm_timer_init();
+
+ omap2_gp_clockevent_init();
+ omap2_gp_clocksource_init();
}
struct sys_timer omap_timer = {
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 8f56c25..d91424e 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -9,7 +9,9 @@ obj-m :=
obj-n :=
obj- :=
+ifeq ($(CONFIG_ARCH_OMAP1),y)
obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
+endif
# OCPI interconnect support for 1710, 1610 and 5912
obj-$(CONFIG_ARCH_OMAP16XX) += ocpi.o
diff --git a/arch/arm/plat-omap/timer32k.c b/arch/arm/plat-omap/timer32k.c
index ea76f19..ce034dc 100644
--- a/arch/arm/plat-omap/timer32k.c
+++ b/arch/arm/plat-omap/timer32k.c
@@ -40,6 +40,7 @@
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/spinlock.h>
+
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/clocksource.h>
@@ -93,8 +94,6 @@ struct sys_timer omap_timer;
#define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
(((nr_jiffies) * (clock_rate)) / HZ)
-#if defined(CONFIG_ARCH_OMAP1)
-
static inline void omap_32k_timer_write(int val, int reg)
{
omap_writew(val, OMAP1_32K_TIMER_BASE + reg);
@@ -120,30 +119,6 @@ static inline void omap_32k_timer_stop(void)
#define omap_32k_timer_ack_irq()
-#elif defined(CONFIG_ARCH_OMAP2)
-
-static struct omap_dm_timer *gptimer;
-
-static inline void omap_32k_timer_start(unsigned long load_val)
-{
- omap_dm_timer_set_load(gptimer, 1, 0xffffffff - load_val);
- omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
- omap_dm_timer_start(gptimer);
-}
-
-static inline void omap_32k_timer_stop(void)
-{
- omap_dm_timer_stop(gptimer);
-}
-
-static inline void omap_32k_timer_ack_irq(void)
-{
- u32 status = omap_dm_timer_read_status(gptimer);
- omap_dm_timer_write_status(gptimer, status);
-}
-
-#endif
-
static void omap_32k_timer_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
@@ -222,23 +197,6 @@ static struct irqaction omap_32k_timer_irq = {
static __init void omap_init_32k_timer(void)
{
- if (cpu_class_is_omap1())
- setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
-
-#ifdef CONFIG_ARCH_OMAP2
- /* REVISIT: Check 24xx TIOCP_CFG settings after idle works */
- if (cpu_is_omap24xx()) {
- gptimer = omap_dm_timer_request_specific(1);
- BUG_ON(gptimer == NULL);
-
- omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ);
- setup_irq(omap_dm_timer_get_irq(gptimer), &omap_32k_timer_irq);
- omap_dm_timer_set_int_enable(gptimer,
- OMAP_TIMER_INT_CAPTURE | OMAP_TIMER_INT_OVERFLOW |
- OMAP_TIMER_INT_MATCH);
- }
-#endif
-
clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
NSEC_PER_SEC,
clockevent_32k_timer.shift);
--
1.5.3.6
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