Hi,
Thanks Syed Khasim for the reply,
> For VGA LCD on 3430SDP we have configured DSS for
> left_margin = 79, /* pixclocks */
> right_margin = 89, /* pixclocks */
> upper_margin = 1, /* line clocks */
> lower_margin = 0, /* line clocks */
> hsync_len = 3, /* pixclocks */
> vsync_len = 2, /* line clocks */
> sync = 1, /* hsync & vsync polarity */
> acb = 0x28, /* AC-bias pin frequency */
> ipc = 1, /* Invert pixel clock */
> onoff = 1; /* HSYNC/VSYNC Pixel clk Control*/
>
I tried with the above values and i am still getting irq errors(gfx
underflow).
The timings corresponding to above values are given below
mode "480x640-49"
# D: 20.600 MHz, H: 31.644 kHz, V: 49.213 Hz
geometry 480 640 480 640 16
timings 48543 89 79 0 1 3 2
accel false
rgba 5/11,6/5,5/0,0/0
endmode
DSS1fclk is at 82.5 Mhz and my prcm settings is PRCM 3 ( Clocking rate
(Crystal/DPLL/MPU): 13.0/660/330 MHz).
That means my dss1Iclk is 110Mhz (L3 is also 110Mhz) is this making any
problem??
> > As with these settings my pixel clock is set to 18.3Mhz and LCD comes up
> > with the linux logo.
> >
> What is the pixel clock required by LCD? Make your FCLK 4 times the pixel clock.
My lcd datasheet says minimum 23 MHz and maximum 26 MHz. But now my
pixel clock is 20Mhz and FCLK is 82.5 (82.5 > 20*4). Is this enough??
> The FIFO settings needs to be adjusted as well, the difference between upper and lower threshold can be made equal to burst size. And keep the high threshold to 0xff.
>
This is matching in my case( burst = 16 X 32 , high= 0xFF ,low =0xC0)
> > If i keep DSS1fclk=55Mhz and pixel_clock=5000 it works without any
> > problem but the vfreq( vertical refresh rate) is very too low for
> > decent viewing in VGA mode.
> >
> 5000?
Yes in the git kernel this 5000 is multiplied by 1000 for setting pixel
clock.
Regards,
Arun c
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