On the OMAP3430 architecture, some clocks are only available on
3430ES1 (e.g., the GFX subsystem, and the 16.8MHz input crystal rate
option) and some clocks are only available on 3430ES2 (e.g., DPLL5,
temp sensor, etc.) Now that OMAP3430ES revision detection is in the
tree, we can flag these so we do not try to initialize clocks that
don't exist on other ES revisions.
To do so, add new clock flags CLOCK_IN_OMAP3430ES1 and
CLOCK_IN_OMAP3430ES2, to be used for clocks that only exist on one
architecture or the other. CLOCK_IN_OMAP343X is still present and
used for clocks which exist on all 343X-level devices. The current
code assumes that production clocks will be identical to 3430ES2
clocks, but this is easy enough to change if necessary.
Signed-off-by: Paul Walmsley <paul@xxxxxxxxx>
---
arch/arm/mach-omap2/clock34xx.c | 9 +++++++
arch/arm/mach-omap2/clock34xx.h | 35 +++++++++++++---------------
arch/arm/mach-omap2/cm_regbits_34xx.h | 42 ++++++++++++++++++----------------
include/asm-arm/arch-omap/clock.h | 4 ++-
4 files changed, 52 insertions(+), 38 deletions(-)
Index: linux-omap/arch/arm/mach-omap2/clock34xx.c
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock34xx.c 2007-12-04 02:31:31.000000000 -0700
+++ linux-omap/arch/arm/mach-omap2/clock34xx.c 2007-12-04 02:31:33.000000000 -0700
@@ -172,6 +172,15 @@
cpu_mask = RATE_IN_343X;
cpu_clkflg = CLOCK_IN_OMAP343X;
clkp = onchip_34xx_clks;
+
+ /*
+ * Update this if there are further clock changes between ES2
+ * and production parts
+ */
+ if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
+ cpu_clkflg |= CLOCK_IN_OMAP3430ES1;
+ else
+ cpu_clkflg |= CLOCK_IN_OMAP3430ES2;
}
clk_init(&omap2_clk_functions);
Index: linux-omap/arch/arm/mach-omap2/clock34xx.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/clock34xx.h 2007-12-04 02:31:31.000000000 -0700
+++ linux-omap/arch/arm/mach-omap2/clock34xx.h 2007-12-04 02:31:33.000000000 -0700
@@ -63,11 +63,10 @@
.recalc = &propagate_rate,
};
-/* 3430ES2 only */
static struct clk virt_16_8m_ck = {
.name = "virt_16_8m_ck",
.rate = 16800000,
- .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES |
+ .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES |
ALWAYS_ENABLED,
.recalc = &propagate_rate,
};
@@ -750,7 +749,7 @@
/* GFX power domain */
-/* REVISIT: These clocks have disappeared in the 3430 ES2 TRM ?? */
+/* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */
static const struct clksel gfx_l3_clksel[] = {
{ .parent = &l3_ick, .rates = gfx_l3_rates },
@@ -766,7 +765,7 @@
.clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
.clksel_mask = OMAP_CLKSEL_GFX_MASK,
.clksel = gfx_l3_clksel,
- .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
+ .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES,
.recalc = &omap2_clksel_recalc,
};
@@ -775,7 +774,7 @@
.parent = &l3_ick,
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
.enable_bit = OMAP_EN_GFX_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
@@ -783,8 +782,8 @@
.name = "gfx_cg1_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
- .enable_bit = OMAP3430_EN_2D_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .enable_bit = OMAP3430ES1_EN_2D_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
@@ -792,8 +791,8 @@
.name = "gfx_cg2_ck",
.parent = &gfx_l3_fck, /* REVISIT: correct? */
.enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
- .enable_bit = OMAP3430_EN_3D_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .enable_bit = OMAP3430ES1_EN_3D_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
@@ -803,8 +802,8 @@
.name = "d2d_26m_fck",
.parent = &sys_ck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP3430_EN_D2D_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .enable_bit = OMAP3430ES1_EN_D2D_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
@@ -1019,8 +1018,8 @@
.name = "fshostusb_fck",
.parent = &core_48m_fck,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
- .enable_bit = OMAP3430_EN_FSHOSTUSB_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
@@ -1343,8 +1342,8 @@
.name = "fac_ick",
.parent = &core_l4_ick,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
- .enable_bit = OMAP3430_EN_FAC_SHIFT,
- .flags = CLOCK_IN_OMAP343X,
+ .enable_bit = OMAP3430ES1_EN_FAC_SHIFT,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &followparent_recalc,
};
@@ -1397,11 +1396,11 @@
.parent = &l4_ick,
.init = &omap2_init_clksel_parent,
.enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
- .enable_bit = OMAP3430_EN_FSHOSTUSB_SHIFT,
+ .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT,
.clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
- .clksel_mask = OMAP3430_CLKSEL_FSHOSTUSB_MASK,
+ .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK,
.clksel = usb_l4_clksel,
- .flags = CLOCK_IN_OMAP343X,
+ .flags = CLOCK_IN_OMAP3430ES1,
.recalc = &omap2_clksel_recalc,
};
Index: linux-omap/include/asm-arm/arch-omap/clock.h
===================================================================
--- linux-omap.orig/include/asm-arm/arch-omap/clock.h 2007-12-04 02:31:31.000000000 -0700
+++ linux-omap/include/asm-arm/arch-omap/clock.h 2007-12-04 02:31:33.000000000 -0700
@@ -129,8 +129,10 @@
#define CLOCK_IN_OMAP16XX (1 << 24)
#define CLOCK_IN_OMAP242X (1 << 25)
#define CLOCK_IN_OMAP243X (1 << 26)
-#define CLOCK_IN_OMAP343X (1 << 27)
+#define CLOCK_IN_OMAP343X (1 << 27) /* clocks common to all 343X */
#define PARENT_CONTROLS_CLOCK (1 << 28)
+#define CLOCK_IN_OMAP3430ES1 (1 << 29) /* 3430ES1 clocks only */
+#define CLOCK_IN_OMAP3430ES2 (1 << 30) /* 3430ES2 clocks only */
/* Clksel_rate flags */
#define DEFAULT_RATE (1 << 0)
Index: linux-omap/arch/arm/mach-omap2/cm_regbits_34xx.h
===================================================================
--- linux-omap.orig/arch/arm/mach-omap2/cm_regbits_34xx.h 2007-12-04 02:31:31.000000000 -0700
+++ linux-omap/arch/arm/mach-omap2/cm_regbits_34xx.h 2007-12-04 02:31:33.000000000 -0700
@@ -23,6 +23,10 @@
#define OMAP3430_EN_MSPRO_SHIFT 23
#define OMAP3430_EN_HDQ (1 << 22)
#define OMAP3430_EN_HDQ_SHIFT 22
+#define OMAP3430ES1_EN_FSHOSTUSB (1 << 5)
+#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
+#define OMAP3430ES1_EN_D2D (1 << 3)
+#define OMAP3430ES1_EN_D2D_SHIFT 3
#define OMAP3430_EN_SSI (1 << 0)
#define OMAP3430_EN_SSI_SHIFT 0
@@ -140,8 +144,8 @@
#define OMAP3430_EN_SHA12_SHIFT 27
#define OMAP3430_EN_DES2 (1 << 26)
#define OMAP3430_EN_DES2_SHIFT 26
-#define OMAP3430_EN_FAC (1 << 8)
-#define OMAP3430_EN_FAC_SHIFT 8
+#define OMAP3430ES1_EN_FAC (1 << 8)
+#define OMAP3430ES1_EN_FAC_SHIFT 8
#define OMAP3430_EN_MAILBOXES (1 << 7)
#define OMAP3430_EN_MAILBOXES_SHIFT 7
#define OMAP3430_EN_OMAPCTRL (1 << 6)
@@ -168,8 +172,8 @@
#define OMAP3430_ST_DES2 (1 << 26)
#define OMAP3430_ST_MSPRO (1 << 23)
#define OMAP3430_ST_HDQ (1 << 22)
-#define OMAP3430_ST_FAC (1 << 8)
-#define OMAP3430_ST_MAILBOXES (1 << 7)
+#define OMAP3430ES1_ST_FAC (1 << 8)
+#define OMAP3430ES1_ST_MAILBOXES (1 << 7)
#define OMAP3430_ST_OMAPCTRL (1 << 6)
#define OMAP3430_ST_SDMA (1 << 2)
#define OMAP3430_ST_SDRC (1 << 1)
@@ -223,18 +227,18 @@
#define OMAP3430_AUTO_MCBSP5_SHIFT 10
#define OMAP3430_AUTO_MCBSP1 (1 << 9)
#define OMAP3430_AUTO_MCBSP1_SHIFT 9
-#define OMAP3430_AUTO_FAC (1 << 8)
-#define OMAP3430_AUTO_FAC_SHIFT 8
+#define OMAP3430ES1_AUTO_FAC (1 << 8)
+#define OMAP3430ES1_AUTO_FAC_SHIFT 8
#define OMAP3430_AUTO_MAILBOXES (1 << 7)
#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
#define OMAP3430_AUTO_OMAPCTRL (1 << 6)
#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
-#define OMAP3430_AUTO_FSHOSTUSB (1 << 5)
-#define OMAP3430_AUTO_FSHOSTUSB_SHIFT 5
+#define OMAP3430ES1_AUTO_FSHOSTUSB (1 << 5)
+#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
#define OMAP3430_AUTO_HSOTGUSB (1 << 4)
#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
-#define OMAP3430_AUTO_D2D (1 << 3)
-#define OMAP3430_AUTO_D2D_SHIFT 3
+#define OMAP3430ES1_AUTO_D2D (1 << 3)
+#define OMAP3430ES1_AUTO_D2D_SHIFT 3
#define OMAP3430_AUTO_SSI (1 << 0)
#define OMAP3430_AUTO_SSI_SHIFT 0
@@ -257,31 +261,31 @@
#define OMAP3430_CLKSEL_GPT11_SHIFT 7
#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
#define OMAP3430_CLKSEL_GPT10_SHIFT 6
-#define OMAP3430_CLKSEL_FSHOSTUSB_SHIFT 4
-#define OMAP3430_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
+#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
#define OMAP3430_CLKSEL_L4_SHIFT 2
#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
#define OMAP3430_CLKSEL_L3_SHIFT 0
#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
/* CM_CLKSTCTRL_CORE */
-#define OMAP3430_CLKTRCTRL_D2D_SHIFT 4
-#define OMAP3430_CLKTRCTRL_D2D_MASK (0x3 << 4)
+#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
+#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
/* CM_CLKSTST_CORE */
-#define OMAP3430_CLKACTIVITY_D2D (1 << 2)
+#define OMAP3430ES1_CLKACTIVITY_D2D (1 << 2)
#define OMAP3430_CLKACTIVITY_L4 (1 << 1)
#define OMAP3430_CLKACTIVITY_L3 (1 << 0)
/* CM_FCLKEN_GFX */
-#define OMAP3430_EN_3D (1 << 2)
-#define OMAP3430_EN_3D_SHIFT 2
-#define OMAP3430_EN_2D (1 << 1)
-#define OMAP3430_EN_2D_SHIFT 1
+#define OMAP3430ES1_EN_3D (1 << 2)
+#define OMAP3430ES1_EN_3D_SHIFT 2
+#define OMAP3430ES1_EN_2D (1 << 1)
+#define OMAP3430ES1_EN_2D_SHIFT 1
/* CM_ICLKEN_GFX specific bits */
--
-
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