On Mon, Feb 19, 2024 at 03:22:14PM +0000, Marc Zyngier wrote:
> From f24638a5f41424faf47f3d9035e6dcbd3800fcb6 Mon Sep 17 00:00:00 2001
> From: Marc Zyngier <maz@xxxxxxxxxx>
> Date: Mon, 19 Feb 2024 15:13:22 +0000
> Subject: [PATCH] arm64: Use Signed/Unsigned enums for TGRAN{4,16,64} and
> VARange
>
> Open-coding the feature matching parameters for LVA/LVA2 leads to
> issues with upcoming changes to the cpufeature code.
>
> By making TGRAN{4,16,64} and VARange signed/unsigned as per the
> architecture, we can use the existing macros, making the feature
> match robust against those changes.
>
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
I think this is the right thing to do; the patch itself looks good to me, so
FWIW:
Acked-by: Mark Rutland <mark.rutland@xxxxxxx>
Mark.
> ---
> arch/arm64/kernel/cpufeature.c | 15 +++------------
> arch/arm64/tools/sysreg | 8 ++++----
> 2 files changed, 7 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 8f9665e8774b..2119e9dd0c4e 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -2791,24 +2791,15 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
> .capability = ARM64_HAS_VA52,
> .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
> .matches = has_cpuid_feature,
> - .field_width = 4,
> #ifdef CONFIG_ARM64_64K_PAGES
> .desc = "52-bit Virtual Addressing (LVA)",
> - .sign = FTR_SIGNED,
> - .sys_reg = SYS_ID_AA64MMFR2_EL1,
> - .field_pos = ID_AA64MMFR2_EL1_VARange_SHIFT,
> - .min_field_value = ID_AA64MMFR2_EL1_VARange_52,
> + ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52)
> #else
> .desc = "52-bit Virtual Addressing (LPA2)",
> - .sys_reg = SYS_ID_AA64MMFR0_EL1,
> #ifdef CONFIG_ARM64_4K_PAGES
> - .sign = FTR_SIGNED,
> - .field_pos = ID_AA64MMFR0_EL1_TGRAN4_SHIFT,
> - .min_field_value = ID_AA64MMFR0_EL1_TGRAN4_52_BIT,
> + ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT)
> #else
> - .sign = FTR_UNSIGNED,
> - .field_pos = ID_AA64MMFR0_EL1_TGRAN16_SHIFT,
> - .min_field_value = ID_AA64MMFR0_EL1_TGRAN16_52_BIT,
> + ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT)
> #endif
> #endif
> },
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index fa3fe0856880..670a33fca3bc 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -1540,16 +1540,16 @@ Enum 35:32 TGRAN16_2
> 0b0010 IMP
> 0b0011 52_BIT
> EndEnum
> -Enum 31:28 TGRAN4
> +SignedEnum 31:28 TGRAN4
> 0b0000 IMP
> 0b0001 52_BIT
> 0b1111 NI
> EndEnum
> -Enum 27:24 TGRAN64
> +SignedEnum 27:24 TGRAN64
> 0b0000 IMP
> 0b1111 NI
> EndEnum
> -Enum 23:20 TGRAN16
> +UnsignedEnum 23:20 TGRAN16
> 0b0000 NI
> 0b0001 IMP
> 0b0010 52_BIT
> @@ -1697,7 +1697,7 @@ Enum 23:20 CCIDX
> 0b0000 32
> 0b0001 64
> EndEnum
> -Enum 19:16 VARange
> +UnsignedEnum 19:16 VARange
> 0b0000 48
> 0b0001 52
> EndEnum
> --
> 2.39.2
>
>
> --
> Without deviation from the norm, progress is not possible.
