Hi all, Commits dbe46b094026 ("RISC-V: Add ptrace support for vectors") ed1a8872ff83 ("soc: renesas: Kconfig: Select the required configs for RZ/Five SoC") f508b0175578 ("cache: Add L2 cache management for Andes AX45MP RISC-V core") 555dd72bc06e ("dt-bindings: cache: andestech,ax45mp-cache: Add DT binding docu dbe46b094026 ("RISC-V: Add ptrace support for vectors") ed1a8872ff83 ("soc: renesas: Kconfig: Select the required configs for RZ/Five SoC") f508b0175578 ("cache: Add L2 cache management for Andes AX45MP RISC-V core") 555dd72bc06e ("dt-bindings: cache: andestech,ax45mp-cache: Add DT binding docu mentation for L2 cache controller") 30bc090f40f8 ("riscv: mm: dma-noncoherent: nonstandard cache operations support") f2863f30d1b0 ("riscv: errata: Add Andes alternative ports") 93e0e2419b65 ("riscv: asm: vendorid_list: Add Andes Technology to the vendors list") eb76e5111881 ("riscv: dma-mapping: switch over to generic implementation") 14be7c16d420 ("riscv: dma-mapping: skip invalidation before bidirectional DMA") fbfc740ced8f ("riscv: dma-mapping: only invalidate after DMA, not flush") b6e3f6e009a1 ("RISC-V: alternative: Remove feature_probe_func") b98673c5b037 ("RISC-V: Probe for unaligned access speed") 26ba042414a3 ("perf: tests: Adapt mmap-basic.c for riscv") 60bd50116484 ("tools: lib: perf: Implement riscv mmap support") 57972127b20e ("Documentation: admin-guide: Add riscv sysctl_perf_user_access") cc4c07c89aad ("drivers: perf: Implement perf event mmap support in the SBI backend") 50be34282905 ("drivers: perf: Implement perf event mmap support in the legacy backend") are missing a Signed-off-by from their committers. -- Cheers, Stephen Rothwell
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