On Thu, Jun 15, 2023 at 12:22:01PM +1000, Stephen Rothwell wrote:
> diff --cc arch/arm64/kernel/cpufeature.c
> index 6ea7f23b1287,f6e3598760f1..000000000000
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@@ -2662,27 -2656,23 +2677,44 @@@ static const struct arm64_cpu_capabilit
> .cpu_enable = cpu_enable_dit,
> ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP)
> },
> + {
> + .desc = "Memory Copy and Memory Set instructions",
> + .capability = ARM64_HAS_MOPS,
> + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + .matches = has_cpuid_feature,
> + .cpu_enable = cpu_enable_mops,
> + ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP)
> + },
> + {
> + .capability = ARM64_HAS_TCR2,
> + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + .matches = has_cpuid_feature,
> + ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP)
> + },
> + {
> + .desc = "Stage-1 Permission Indirection Extension (S1PIE)",
> + .capability = ARM64_HAS_S1PIE,
> + .type = ARM64_CPUCAP_BOOT_CPU_FEATURE,
> + .matches = has_cpuid_feature,
> + ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP)
> + },
> + {
> + .desc = "Enhanced Virtualization Traps",
> + .capability = ARM64_HAS_EVT,
> + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + .sys_reg = SYS_ID_AA64MMFR2_EL1,
> + .sign = FTR_UNSIGNED,
> + .field_pos = ID_AA64MMFR2_EL1_EVT_SHIFT,
> + .field_width = 4,
> + .min_field_value = ID_AA64MMFR2_EL1_EVT_IMP,
> + .matches = has_cpuid_feature,
> + },
> + {
> + .desc = "VHE for hypervisor only",
> + .capability = ARM64_KVM_HVHE,
> + .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> + .matches = hvhe_possible,
> + },
> {},
> };
This looks fine. Thanks Stephen.
--
Catalin
