On Thu, 2020-12-10 at 08:30 +0000, Marc Zyngier wrote: > We reset the guest's view of PMCR_EL0 unconditionally, based on > the host's view of this register. It is however legal for an > imnplementation not to provide any PMU, resulting in an UNDEF. > > The obvious fix is to skip the reset of this shadow register > when no PMU is available, sidestepping the issue entirely. > If no PMU is available, the guest is not able to request > a virtual PMU anyway, so not doing nothing is the right thing > to do! > > It is unlikely that this bug can hit any HW implementation > though, as they all provide a PMU. It has been found using nested > virt with the host KVM not implementing the PMU itself. > > Fixes: ab9468340d2bc ("arm64: KVM: Add access handler for PMCR register") > Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> Reverting this commit on the top of today's linux-next fixed a qemu-kvm coredump issue on TX2 while starting a guest. - host kernel .config: https://cailca.coding.net/public/linux/mm/git/files/master/arm64.config # /usr/libexec/qemu-kvm -name ubuntu-20.04-server-cloudimg -cpu host -smp 2 -m 2g -drive if=none,format=qcow2,file=./ubuntu-20.04-server-cloudimg.qcow2,id=hd -device virtio-scsi -device scsi-hd,drive=hd -cdrom ./ubuntu-20.04-server-cloudimg.iso -bios /usr/share/AAVMF/AAVMF_CODE.fd -M gic-version=host -nographic -nic user,model=virtio,hostfwd=tcp::2222-:22 qemu-kvm: /builddir/build/BUILD/qemu-4.2.0/target/arm/helper.c:1812: pmevcntr_rawwrite: Assertion `counter < pmu_num_counters(env)' failed. > --- > arch/arm64/kvm/sys_regs.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index bc15246775d0..6c64d010102b 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -923,6 +923,10 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const > struct sys_reg_desc *r) > { > u64 pmcr, val; > > + /* No PMU available, PMCR_EL0 may UNDEF... */ > + if (!kvm_arm_support_pmu_v3()) > + return; > + > pmcr = read_sysreg(pmcr_el0); > /* > * Writable bits of PMCR_EL0 (ARMV8_PMU_PMCR_MASK) are reset to UNKNOWN