On Wed, Aug 7, 2019 at 9:03 AM Koenig, Christian <Christian.Koenig@xxxxxxx> wrote: > > Am 07.08.19 um 15:00 schrieb Christoph Hellwig: > > On Wed, Aug 07, 2019 at 10:55:01AM +0000, Koenig, Christian wrote: > >>>> Essentially writeq/readq doesn't seems to be available on all > >>>> architectures either. > >>> writeq/readq are provided whenever the CPU actually supports 64-bit > >>> atomic loads and stores. > >> Is there a config option which we can make the driver depend on? > >> > >> I mean that ARM doesn't support 64bit atomic loads and stores on MMIO is > >> quite a boomer for us. > > The model is to cheack if readq/writeq are defined, and if not to > > include the one of io-64-nonatomic-hi-lo.h or io-64-nonatomic-lo-hi.h. > > The reason for that is that hardware is supposed to be able to deal with > > two 32-bit writes, but it depends on the hardware if the lower or upper > > half is what commits the write. > > Read, but as I understood Tao change this is not the case here. > Otherwise we would just use our WREG32/RREG32 macros in the driver. > > Tao, please explain why exactly we need the WREG64/RREG64 change which > caused this. We use this for doorbells as well which is also MMIO. Basically we have the requirement to read or write the full 64 bits in one operation. E.g., for 64-bit doorbells, the entire register is the trigger so if we do it as two writes, we'll miss half the update. In the case of some error counter registers, reading the register will clear the value so we need to read out the full value or we lose the half the value. This works properly on x86 and AMD64. Alex > > Christian. > > > > > The only 32-bit platform that claims support for readq/writeq is sh, > > and I have doubts if that actually works as expected. > > _______________________________________________ > amd-gfx mailing list > amd-gfx@xxxxxxxxxxxxxxxxxxxxx > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
