Hi Mark,
In commit
019194933339 ("spi: tegra114: reset controller on probe")
Fixes tag
Fixes: SPI driver can be built as module so perform SPI controller reset
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In commit
f4ce428c41fb ("spi: tegra114: configure dma burst size to fifo trig level")
Fixes tag
Fixes: Configure DMA burst size to be same as SPI TX/RX trigger levels
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In commit
c4fc9e5b28ff ("spi: tegra114: flush fifos")
Fixes tag
Fixes: Flush TX and RX FIFOs before start of new transfer and on FIFO
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In commit
32bd1a9551ca ("spi: tegra114: terminate dma and reset on transfer timeout")
Fixes tag
Fixes: terminate DMA and perform controller reset on transfer timeout
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In commit
1a89ac5b9189 ("spi: tegra114: fix for unpacked mode transfers")
Fixes tag
Fixes: computation of actual bytes to fill/receive in/from FIFO in unpacked
has these problem(s):
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In commit
7b3d10cdf54b ("spi: tegra114: clear packed bit for unpacked mode")
Fixes tag
Fixes: Clear packed bit when not using packed mode.
has these problem(s):
- No SHA1 recognised
--
Cheers,
Stephen Rothwell
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