Hi Ralf,
Today's linux-next merge of the mips tree got a conflict in
arch/mips/mm/tlb-r4k.c between commit 9ead8632bbf4 ("MIPS: Fix
C0_Pagegrain[IEC] support") from Linus' tree and commit a5770df09541
("MIPS: Add set/clear CP0 macros for PageGrain register") from the mips
tree.
I fixed it up (see below) and can carry the fix as necessary (no action
is required).
--
Cheers,
Stephen Rothwell sfr@xxxxxxxxxxxxxxxx
diff --cc arch/mips/mm/tlb-r4k.c
index 30639a6e9b8c,b2afa49beab0..000000000000
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@@ -485,13 -485,11 +485,14 @@@ static void r4k_tlb_configure(void
* Enable the no read, no exec bits, and enable large virtual
* address.
*/
+ u32 pg = PG_RIE | PG_XIE;
++
++ if (cpu_has_rixiex)
++ pg |= PG_IEC;
#ifdef CONFIG_64BIT
- set_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA);
-#else
- set_c0_pagegrain(PG_RIE | PG_XIE);
+ pg |= PG_ELPA;
#endif
- if (cpu_has_rixiex)
- pg |= PG_IEC;
- write_c0_pagegrain(pg);
++ set_c0_pagegrain(pg);
}
temp_tlb_entry = current_cpu_data.tlbsize - 1;
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