linux-next: manual merge of the pinctrl tree with Linus' tree

[Stephen Rothwell <sfr@xxxxxxxxxxxxxxxx>]

Hi Linus,

Today's linux-next merge of the pinctrl tree got a conflict in
drivers/pinctrl/pinctrl-sunxi.c between commit 1bee963db9dd ("pinctrl:
sunxi: Add spinlocks") from Linus' tree and commit 03b054e9696c
("pinctrl: Pass all configs to driver on pin_config_set()") from the
pinctrl tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

-- 
Cheers,
Stephen Rothwell                    sfr@xxxxxxxxxxxxxxxx

diff --cc drivers/pinctrl/pinctrl-sunxi.c
index 94716c7,8dbd465..0000000
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@@ -282,56 -282,47 +283,60 @@@ static int sunxi_pconf_group_set(struc
  	u32 val, mask;
  	u16 strength;
  	u8 dlevel;
+ 	int i;
  
- 	switch (pinconf_to_config_param(config)) {
- 	case PIN_CONFIG_DRIVE_STRENGTH:
- 		strength = pinconf_to_config_argument(config);
- 		if (strength > 40)
- 			return -EINVAL;
- 		/*
- 		 * We convert from mA to what the register expects:
- 		 *   0: 10mA
- 		 *   1: 20mA
- 		 *   2: 30mA
- 		 *   3: 40mA
- 		 */
- 		dlevel = strength / 10 - 1;
- 
- 		spin_lock_irqsave(&pctl->lock, flags);
- 
- 		val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
- 	        mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
- 		writel((val & ~mask) | dlevel << sunxi_dlevel_offset(g->pin),
- 			pctl->membase + sunxi_dlevel_reg(g->pin));
- 
- 		spin_unlock_irqrestore(&pctl->lock, flags);
- 		break;
- 	case PIN_CONFIG_BIAS_PULL_UP:
- 		spin_lock_irqsave(&pctl->lock, flags);
+ 	for (i = 0; i < num_configs; i++) {
+ 		switch (pinconf_to_config_param(configs[i])) {
+ 		case PIN_CONFIG_DRIVE_STRENGTH:
+ 			strength = pinconf_to_config_argument(configs[i]);
+ 			if (strength > 40)
+ 				return -EINVAL;
+ 			/*
+ 			 * We convert from mA to what the register expects:
+ 			 *   0: 10mA
+ 			 *   1: 20mA
+ 			 *   2: 30mA
+ 			 *   3: 40mA
+ 			 */
+ 			dlevel = strength / 10 - 1;
++
++			spin_lock_irqsave(&pctl->lock, flags);
++
+ 			val = readl(pctl->membase + sunxi_dlevel_reg(g->pin));
+ 			mask = DLEVEL_PINS_MASK << sunxi_dlevel_offset(g->pin);
+ 			writel((val & ~mask)
+ 				| dlevel << sunxi_dlevel_offset(g->pin),
+ 				pctl->membase + sunxi_dlevel_reg(g->pin));
++
++			spin_unlock_irqrestore(&pctl->lock, flags);
+ 			break;
+ 		case PIN_CONFIG_BIAS_PULL_UP:
++			spin_lock_irqsave(&pctl->lock, flags);
 +
- 		val = readl(pctl->membase + sunxi_pull_reg(g->pin));
- 		mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
- 		writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
- 			pctl->membase + sunxi_pull_reg(g->pin));
+ 			val = readl(pctl->membase + sunxi_pull_reg(g->pin));
+ 			mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
+ 			writel((val & ~mask) | 1 << sunxi_pull_offset(g->pin),
+ 				pctl->membase + sunxi_pull_reg(g->pin));
 +
- 		spin_unlock_irqrestore(&pctl->lock, flags);
- 		break;
- 	case PIN_CONFIG_BIAS_PULL_DOWN:
- 		spin_lock_irqsave(&pctl->lock, flags);
++			spin_unlock_irqrestore(&pctl->lock, flags);
+ 			break;
+ 		case PIN_CONFIG_BIAS_PULL_DOWN:
++			spin_lock_irqsave(&pctl->lock, flags);
 +
- 		val = readl(pctl->membase + sunxi_pull_reg(g->pin));
- 		mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
- 		writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
- 			pctl->membase + sunxi_pull_reg(g->pin));
+ 			val = readl(pctl->membase + sunxi_pull_reg(g->pin));
+ 			mask = PULL_PINS_MASK << sunxi_pull_offset(g->pin);
+ 			writel((val & ~mask) | 2 << sunxi_pull_offset(g->pin),
+ 				pctl->membase + sunxi_pull_reg(g->pin));
 +
- 		spin_unlock_irqrestore(&pctl->lock, flags);
- 		break;
- 	default:
- 		break;
- 	}
++			spin_unlock_irqrestore(&pctl->lock, flags);
+ 			break;
+ 		default:
+ 			break;
+ 		}
  
- 	/* cache the config value */
- 	g->config = config;
+ 		/* cache the config value */
+ 		g->config = configs[i];
+ 	} /* for each config */
  
  	return 0;
  }

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