Hi Catalin,
Today's linux-next merge of the arm-lpae tree got a conflict in
arch/arm/kernel/sleep.S between commit 805f72ef00a4 ("ARM: pm:
preallocate a page table for suspend/resume") (and later ones) from the
arm tree and commit 787dad4a57fb ("ARM: LPAE: add ISBs around MMU
enabling code") from the arm-lpae tree.
I attempted to fix it up (see below) and can carry the fix as necessary.
There are also other conflicts due to the same changes existaing in each
of these trees as different commits. Maybe some rebase or cleanup of the
arm-lpae tree is required.
--
Cheers,
Stephen Rothwell sfr@xxxxxxxxxxxxxxxx
diff --cc arch/arm/kernel/sleep.S
index 020e99c,ecece65..0000000
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@@ -52,17 -67,35 +52,19 @@@ ENDPROC(cpu_suspend_abort
/*
* r0 = control register value
- * r1 = v:p offset (preserved by cpu_do_resume)
- * r2 = phys page table base
- * r3 = L1 section flags
*/
+ .align 5
ENTRY(cpu_resume_mmu)
- adr r4, cpu_resume_turn_mmu_on
- mov r4, r4, lsr #20
- orr r3, r3, r4, lsl #20
- ldr r5, [r2, r4, lsl #2] @ save old mapping
- str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code
- sub r2, r2, r1
ldr r3, =cpu_resume_after_mmu
- bic r1, r0, #CR_C @ ensure D-cache is disabled
- b cpu_resume_turn_mmu_on
-ENDPROC(cpu_resume_mmu)
- .ltorg
- .align 5
-cpu_resume_turn_mmu_on:
+ instr_sync
- mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc
- mrc p15, 0, r1, c0, c0, 0 @ read id reg
+ mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
+ mrc p15, 0, r0, c0, c0, 0 @ read id reg
+ instr_sync
- mov r1, r1
- mov r1, r1
+ mov r0, r0
+ mov r0, r0
mov pc, r3 @ jump to virtual address
-ENDPROC(cpu_resume_turn_mmu_on)
+ENDPROC(cpu_resume_mmu)
cpu_resume_after_mmu:
- str r5, [r2, r4, lsl #2] @ restore old mapping
- mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache
bl cpu_init @ restore the und/abt/irq banked regs
mov r0, #0 @ return zero on success
ldmfd sp!, {r4 - r11, pc}
--
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