Re: Route cache performance under stress

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   From: Andi Kleen <ak@suse.de>
   Date: Mon, 9 Jun 2003 11:47:34 +0200
   
   gcc will generate a lot better code for the memsets if you can tell
   it somehow they are long aligned and a multiple of 8 bytes.

True, but the real bug is that we're initializing any of this
crap here at all.  Right now we write over the same cachelines
3 or so times.  It should really just happen once.
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