Re: [PATCH] mtd: rawnand: Non ONFI specialized timing support

[Miquel Raynal <miquel.raynal@xxxxxxxxxxx>]

Hi Rickard,

+ boris

Rickard Andersson <rickaran@xxxxxxxx> wrote on Wed, 22 Apr 2020
14:18:00 +0200:

> From: Rickard x Andersson <rickaran@xxxxxxxx>
> 
> The Kioxia/Toshiba TH58NVG2S3HBAI4 NAND memory is not a
> ONFI compliant memory. The timings of that memory are quite
> close to ONFI mode 4 but is breaking that spec.
> 
> This patch adds a special table with timings that can be
> used for non ONFI memories.
> 
> Erase block read speed is increased from 6739 KiB/s to
> 13260 KiB/s. Erase block write speed is increased from
> 3004 KiB/s to 3872 KiB/s.
> 
> Tested on IMX6ULL which has a NAND controller supporting
> EDO mode.

I am convinced about the idea of tweaking non-ONFI timings on a
per-chip basis to enhance their throughput, but I think we should do
this another way. 

What we could have is a way, for NAND manufacturer drivers, to overload
the timings. This way, Kioxia timings remain in the Toshiba driver.

I quickly prepared a small series [1], it is untested but it will
hopefully help you adapt your patch. You just have to set the
chip->init_data_interface() hook from the Toshiba driver at init time.
This hook is supposed to update the whole data interface structure and
also call chip->controller.ops() to verify it is supported by the
controller.

[1] https://github.com/miquelraynal/linux/tree/perso/nand-next/timings

Thanks,
Miquèl

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