Re: [PATCH v3 4/5] mtd: spi-nor: Add SR 4bit block protection support

[<Tudor.Ambarus@xxxxxxxxxxxxx>]

On Monday, March 23, 2020 8:33:19 PM EET Michael Walle wrote:
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> Am 2020-03-23 10:24, schrieb Tudor.Ambarus@xxxxxxxxxxxxx:
> > From: Jungseung Lee <js07.lee@xxxxxxxxxxx>
> > 
> > Currently, we are supporting block protection only for flash chips with
> > 3 block protection bits (BP0-2) in the SR register.
> > 
> > Enable block protection support for flashes with 4 block protection
> > bits
> > (BP0-3).
> > 
> > Add a flash_info flag for flashes that describe 4 block protection
> > bits.
> > Add another flash_info flag for flashes in which BP3 bit is not
> > adjacent
> > to the BP0-2 bits.
> > 
> > Signed-off-by: Jungseung Lee <js07.lee@xxxxxxxxxxx>
> > Reviewed-by: Michael Walle <michael@xxxxxxxx>
> > Tested-by: Michael Walle <michael@xxxxxxxx>
> > [ta:
> > - introduce spi_nor_get_sr_bp_mask(), spi_nor_get_sr_tb_mask()
> > - drop Micron n25q512ax3 / BP0-3) boilerplate description
> 
> that was actually a comment on my side some time ago. Because the
> current
> example isn't really good and lacks the second case (which is added by
> this patch).
> 

I didn't like the example that was introduced by Jungseung because of the last 
column, the "Protected Portion" -> it focuses on Upper/Lower 1/pow(2, n). I 
think it is better to replace the "Protected Portion" column with a "Protected 
Block(s)" column (see a winbond datasheet), in order to be in sync with how 
the code looks now.

It's true that the current example has the same problem. Would you care to 
send a patch to replace the current example? (keeping two examples would be 
too much). Or maybe remove the example entirely?

Also, would you please review 1/5 as well? I need an agreement on that before 
applying the series.

Cheers,
ta


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