Re: [PATCH v3 2/3] mtd: spi-nor: add 4bit block protection support

[<Tudor.Ambarus@xxxxxxxxxxxxx>]

Hi, Jungseung,

On Wednesday, January 22, 2020 1:42:00 PM EET Jungseung Lee wrote:

cut

> > > > +#define SPI_NOR_BP3_SR_BIT6    BIT(18) /*
> > > > +                                        * BP3 is bit 6 of status
> > > > register.
> > > > +                                        * Must be used with
> > > 
> > > Are we safe to replace SPI_NOR_TB_SR_BIT6 and SPI_NOR_BP3_SR_BIT6
> > > with a
> > > SPI_NOR_SR_TB_BIT6_BP3_BIT5? Or maybe with a
> > > SPI_NOR_SR_BP3_BIT6_TB_BIT5, how
> > > is more convenient?
> > 
> > Let's think about some flash in which BP0-3 exists in the status
> > register but TB exists in another register.
> > for example, mx25u12835f.
> > I haven't tested yet, but according to the datasheet, I think this
> > patch can support 4bit block protection for the flash.
> > 
> > In order to embrace the case, how about letting them as It is.
> > Is there any suggestion?

Ok, this info should go in the commit message, together with details about 
which flashes were tested.

I didn't know that the TB bit can be defined in the Configuration register. 
This means that your suggestion with dedicated macros for BP3 and TB is fine.

I looked a bit over your patches, they are in a pretty good shape. I saw 
something that can be improved on patch 2/3, but I didn't manage to finish the 
review. Your patches are the first on my TODO list, but now I'm a bit busy. I 
hope that I'll come with a complete review by the end of the next week. I'm 
going to do tests on few flashes too, to make sure that BP0-2 was not 
affected.

In the meantime, maybe Michael or John can review/test your patches, they 
showed interest in BP0-3 support.

Cheers,
ta


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