RE: [EXT] [PATCH 1/3] mtd: spi-nor: Split mt25qu512a (n25q512a) entry into two

[Ashish Kumar <ashish.kumar@xxxxxxx>]

Hi Vignesh,

> -----Original Message-----
> From: Vignesh Raghavendra <vigneshr@xxxxxx>
> Sent: Thursday, December 5, 2019 12:30 PM
> To: Tudor Ambarus <tudor.ambarus@xxxxxxxxxxxxx>
> Cc: Miquel Raynal <miquel.raynal@xxxxxxxxxxx>; Richard Weinberger
> <richard@xxxxxx>; Vignesh Raghavendra <vigneshr@xxxxxx>; Ashish Kumar
> <ashish.kumar@xxxxxxx>; linux-mtd@xxxxxxxxxxxxxxxxxxx; linux-
> kernel@xxxxxxxxxxxxxxx; John Garry <john.garry@xxxxxxxxxx>
> Subject: [EXT] [PATCH 1/3] mtd: spi-nor: Split mt25qu512a (n25q512a) entry
> into two
> 
> Caution: EXT Email
> 
> mt25q family is different from n25q family of devices, even though manf ID
> and device IDs are same. mt25q flash has bit 6 set in 5th byte of READ ID
> response which can be used to distinguish it from n25q variant.
> mt25q flashes support stateless 4 Byte addressing opcodes where as n25q
> flashes don't. Therefore, have two separate entries for mt25qu512a and
> n25q512a.
> 
> Fixes: 9607af6f857f ("mtd: spi-nor: Rename "n25q512a" to "mt25qu512a
> (n25q512a)"")
> Signed-off-by: Vignesh Raghavendra <vigneshr@xxxxxx>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index f4afe123e9dc..01efea022990 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -2459,15 +2459,16 @@ static const struct flash_info spi_nor_ids[] = {
>         { "n25q256a",    INFO(0x20ba19, 0, 64 * 1024,  512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { "n25q256ax1",  INFO(0x20bb19, 0, 64 * 1024,  512, SECT_4K |
> SPI_NOR_QUAD_READ) },
>         { "n25q512ax3",  INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ) },
> +       { "mt25qu512a",  INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
> +                              SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> +                              SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
It seems you have moved back to my original patch [1], wrt mt25qu512a.

Regards
Ashish  
> +       { "n25q512a",    INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K |
> +                             SPI_NOR_QUAD_READ) },
>         { "n25q00",      INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>         { "n25q00a",     INFO(0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>         { "mt25ql02g",   INFO(0x20ba22, 0, 64 * 1024, 4096,
>                               SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
>                               NO_CHIP_ERASE) },
> -       { "mt25qu512a (n25q512a)", INFO(0x20bb20, 0, 64 * 1024, 1024,
> -                                       SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> -                                       SPI_NOR_QUAD_READ |
> -                                       SPI_NOR_4B_OPCODES) },
>         { "mt25qu02g",   INFO(0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> 
>         /* Micron */
> --
> 2.24.0
[1]: http://patchwork.ozlabs.org/patch/1146197/


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