Re: flash_lock issue for n25q 128mb spi nor part

[<Tudor.Ambarus@xxxxxxxxxxxxx>]

Hi, John,

On 12/2/19 7:28 PM, John Garry wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Hi guys,
> 
> I am testing the following driver on top of Linus' master branch with a
> n25q128a11 part:

I understand the you enabled locking support for this flash on your side,
because in mainline it is not yet there.

Be aware that this flash has BP3 support, and in mainline we support for now
just BP0-BP2, so just a partial lock can be achieved, and it depends on what you
tried to lock. It will be helpful to tell how you enabled the locking and what
commands did you use.

> 
> https://lore.kernel.org/linux-mtd/1572886297-45400-3-git-send-email-john.garry@xxxxxxxxxx/
> 
> I am finding flash lock is not working. Even after a “successful” lock,
> flash_lock is reporting flash is unlocked. And I can still write to the
> flash.
> 
> I find that since 39d1e3340c73 ("mtd: spi-nor: Fix clearing of QE bit on
> lock()/unlock()"), we're using a 16b SR for this part in the driver, but
> this part only has a 8b SR.
> 
> This hack fixes the problem for me:
> 
> @ -4691,7 +4691,7 @@ static void spi_nor_info_init_params(struct spi_nor
> *nor)
> params->set_4byte = spansion_set_4byte;
> params->setup = spi_nor_default_setup;
> /* Default to 16-bit Write Status (01h) Command */
> - nor->flags |= SNOR_F_HAS_16BIT_SR;
> +// nor->flags |= SNOR_F_HAS_16BIT_SR;

This means that bfpt is not parsed. You can confirm this by running with the
patch from below.

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index f4afe123e9dc..735cd5202598 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -3545,8 +3545,11 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
                return err;

        /* Fix endianness of the BFPT DWORDs. */
-       for (i = 0; i < BFPT_DWORD_MAX; i++)
+       for (i = 0; i < BFPT_DWORD_MAX; i++) {
                bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]);
+               dev_err(nor->dev, "bfpt.dwords[%d] = %08x\n", i,
+                       bfpt.dwords[i]);
+       }

        /* Number of address bytes. */
        switch (bfpt.dwords[BFPT_DWORD(1)] & BFPT_DWORD1_ADDRESS_BYTES_MASK) {
@@ -3649,6 +3652,9 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
        params->page_size >>= BFPT_DWORD11_PAGE_SIZE_SHIFT;
        params->page_size = 1U << params->page_size;

+       dev_err(nor->dev, "bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK =
%08x\n",
+               bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK);
+
        /* Quad Enable Requirements. */
        switch (bfpt.dwords[BFPT_DWORD(15)] & BFPT_DWORD15_QER_MASK) {
        case BFPT_DWORD15_QER_NONE:
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