Re: [PATCH] spi-nor: intel-spi: Whitelist 4B read commands

[<Tudor.Ambarus@xxxxxxxxxxxxx>]

Mika,

Would you please review the patch from below?

Thanks,
ta

On 07/12/2019 03:14 PM, Sverdlin, Alexander (Nokia - DE/Ulm) wrote:
> External E-Mail
> 
> 
> From: Alexander Sverdlin <alexander.sverdlin@xxxxxxxxx>
> 
> spi-nor.c issues 4B commands for some Flash chips bigger than 16Mbytes.
> Xeon(R) D-1500 documentation mentions its Integrated PCH Logic supports
> Flash chips up to 64Mbytes.
> D-1500 Integrated PCH documenation however has inconsistencies regarding
> FADDR register width and says nothing about particular commands issued
> to support 64Mbytes of Flash.
> 
> Nevetheless the tests on Xeon(R) CPU D-1548 with 512Mbit Flash chips
> Macronix MX25L51245G and Micron MT25QL512A showed that erase, write and
> read operations work just fine after SPINOR_OP_READ_4B and
> SPINOR_OP_READ_FAST_4B are white-listed (currently only
> SPINOR_OP_READ_FAST_4B is used and only for Macronix).
> 
> Signed-off-by: Alexander Sverdlin <alexander.sverdlin@xxxxxxxxx>
> ---
>  drivers/mtd/spi-nor/intel-spi.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/intel-spi.c b/drivers/mtd/spi-nor/intel-spi.c
> index 1ccf23f..43e55a2e 100644
> --- a/drivers/mtd/spi-nor/intel-spi.c
> +++ b/drivers/mtd/spi-nor/intel-spi.c
> @@ -621,6 +621,8 @@ static ssize_t intel_spi_read(struct spi_nor *nor, loff_t from, size_t len,
>  	switch (nor->read_opcode) {
>  	case SPINOR_OP_READ:
>  	case SPINOR_OP_READ_FAST:
> +	case SPINOR_OP_READ_4B:
> +	case SPINOR_OP_READ_FAST_4B:
>  		break;
>  	default:
>  		return -EINVAL;
> 
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