Currently, we are supporting block protection only for
flash chips with 3 block protection bits in the SR register.
This patch enables block protection support for some flash with
4 block protection bits(bp0-3).
Because this feature is not universal to all flash that support
lock/unlock, control it via a new flag.
Signed-off-by: Jungseung Lee <js07.lee@xxxxxxxxxxx>
---
drivers/mtd/spi-nor/spi-nor.c | 87 +++++++++++++++++++++++++++--------
include/linux/mtd/spi-nor.h | 5 ++
2 files changed, 74 insertions(+), 18 deletions(-)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index dd12d3c83029..0d0b92de62db 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -96,6 +96,7 @@ enum spi_nor_pp_command_index {
struct spi_nor_flash_parameter {
u64 size;
u32 page_size;
+ u16 n_sectors;
struct spi_nor_hwcaps hwcaps;
struct spi_nor_read_command reads[SNOR_CMD_READ_MAX];
@@ -250,7 +251,7 @@ struct flash_info {
u16 page_size;
u16 addr_width;
- u16 flags;
+ u32 flags;
#define SECT_4K BIT(0) /* SPINOR_OP_BE_4K works uniformly */
#define SPI_NOR_NO_ERASE BIT(1) /* No erase command needed */
#define SST_WRITE BIT(2) /* use SST byte programming */
@@ -279,6 +280,7 @@ struct flash_info {
#define SPI_NOR_SKIP_SFDP BIT(13) /* Skip parsing of SFDP tables */
#define USE_CLSR BIT(14) /* use CLSR command */
#define SPI_NOR_OCTAL_READ BIT(15) /* Flash supports Octal Read */
+#define SPI_NOR_HAS_BP3 BIT(16) /* use 4 bits filed for block protect */
/* Part specific fixup hooks. */
const struct spi_nor_fixups *fixups;
@@ -1088,21 +1090,43 @@ static void stm_get_locked_range(struct spi_nor *nor, u8 sr, loff_t *ofs,
uint64_t *len)
{
struct mtd_info *mtd = &nor->mtd;
- u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
- int pow;
+ u8 sr_masked, mask, tmp;
+ int pow = 0;
- if (!(sr & mask)) {
+ if (nor->flags & SNOR_F_HAS_SR_BP3)
+ mask = SR_BP3_BIT6 | SR_BP2 | SR_BP1 | SR_BP0;
+ else
+ mask = SR_BP2 | SR_BP1 | SR_BP0;
+
+ sr_masked = sr & mask;
+
+ if (!sr_masked) {
/* No protection */
*ofs = 0;
*len = 0;
- } else {
- pow = ((sr & mask) ^ mask) >> SR_BP_SHIFT;
- *len = mtd->size >> pow;
- if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB_BIT5)
- *ofs = 0;
+ return;
+ }
+
+ if (nor->flags & SNOR_F_HAS_SR_BP3) {
+ if (sr_masked & SR_BP3_BIT6)
+ tmp = (sr_masked & ~SR_BP3_BIT6) | BIT(5);
else
- *ofs = mtd->size - *len;
+ tmp = sr_masked;
+
+ tmp >>= SR_BP_SHIFT;
+
+ if (ilog2(nor->n_sectors) >= tmp)
+ pow = ilog2(nor->n_sectors) - tmp + 1;
+ } else {
+ pow = (sr_masked ^ mask) >> SR_BP_SHIFT;
}
+
+ *len = mtd->size >> pow;
+
+ if (nor->flags & SNOR_F_HAS_SR_TB && sr & SR_TB_BIT5)
+ *ofs = 0;
+ else
+ *ofs = mtd->size - *len;
}
/*
@@ -1176,12 +1200,16 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
struct mtd_info *mtd = &nor->mtd;
int status_old, status_new;
- u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
- u8 pow, val;
+ u8 mask, pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
+ if (nor->flags & SNOR_F_HAS_SR_BP3)
+ mask = SR_BP3_BIT6 | SR_BP2 | SR_BP1 | SR_BP0;
+ else
+ mask = SR_BP2 | SR_BP1 | SR_BP0;
+
status_old = read_sr(nor);
if (status_old < 0)
return status_old;
@@ -1221,7 +1249,16 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
* pow = ceil(log2(size / len)) = log2(size) - floor(log2(len))
*/
pow = ilog2(mtd->size) - ilog2(lock_len);
- val = mask - (pow << SR_BP_SHIFT);
+
+ if (nor->flags & SNOR_F_HAS_SR_BP3) {
+ val = ilog2(nor->n_sectors) - pow + 1;
+ val = val << SR_BP_SHIFT;
+ if (val & BIT(5))
+ val = (val & ~BIT(5)) | SR_BP3_BIT6;
+ } else {
+ val = mask - (pow << SR_BP_SHIFT);
+ }
+
if (val & ~mask)
return -EINVAL;
/* Don't "lock" with no region! */
@@ -1256,12 +1293,16 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
{
struct mtd_info *mtd = &nor->mtd;
int status_old, status_new;
- u8 mask = SR_BP2 | SR_BP1 | SR_BP0;
- u8 pow, val;
+ u8 mask, pow, val;
loff_t lock_len;
bool can_be_top = true, can_be_bottom = nor->flags & SNOR_F_HAS_SR_TB;
bool use_top;
+ if (nor->flags & SNOR_F_HAS_SR_BP3)
+ mask = SR_BP3_BIT6 | SR_BP2 | SR_BP1 | SR_BP0;
+ else
+ mask = SR_BP2 | SR_BP1 | SR_BP0;
+
status_old = read_sr(nor);
if (status_old < 0)
return status_old;
@@ -1303,13 +1344,19 @@ static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
pow = ilog2(mtd->size) - order_base_2(lock_len);
if (lock_len == 0) {
val = 0; /* fully unlocked */
+ } else if (nor->flags & SNOR_F_HAS_SR_BP3) {
+ val = ilog2(nor->n_sectors) - pow + 1;
+ val = val << SR_BP_SHIFT;
+ if (val & BIT(5))
+ val = (val & ~BIT(5)) | SR_BP3_BIT6;
} else {
val = mask - (pow << SR_BP_SHIFT);
- /* Some power-of-two sizes are not supported */
- if (val & ~mask)
- return -EINVAL;
}
+ /* Some power-of-two sizes are not supported */
+ if (val & ~mask)
+ return -EINVAL;
+
status_new = (status_old & ~mask & ~SR_TB_BIT5) | val;
/* Don't protect status register if we're fully unlocked */
@@ -3580,6 +3627,7 @@ static int spi_nor_init_params(struct spi_nor *nor,
memset(params, 0, sizeof(*params));
/* Set SPI NOR sizes. */
+ params->n_sectors = info->n_sectors;
params->size = (u64)info->sector_size * info->n_sectors;
params->page_size = info->page_size;
@@ -4091,12 +4139,15 @@ int spi_nor_scan(struct spi_nor *nor, const char *name,
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
if (info->flags & USE_CLSR)
nor->flags |= SNOR_F_USE_CLSR;
+ if (info->flags & SPI_NOR_HAS_BP3)
+ nor->flags |= SNOR_F_HAS_SR_BP3;
if (info->flags & SPI_NOR_NO_ERASE)
mtd->flags |= MTD_NO_ERASE;
mtd->dev.parent = dev;
nor->page_size = params.page_size;
+ nor->n_sectors = params.n_sectors;
mtd->writebufsize = nor->page_size;
if (np) {
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index b8f4439c30b1..751b6ea0776a 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -129,7 +129,9 @@
#define SR_SRWD BIT(7) /* SR write protect */
/* Used for STM and Micron flashes */
#define SR_TB_BIT5 BIT(5) /* Top/Bottom protect */
+#define SR_BP3_BIT6 BIT(6) /* Block protect 3 */
/* Used for Winbond and GigaDevice flashes */
+#define SR_BP3_BIT5 BIT(5) /* Block protect 3 */
#define SR_TB_BIT6 BIT(6) /* Top/Bottom protect */
#define SR_BP_SHIFT 2
@@ -249,6 +251,7 @@ enum spi_nor_option_flags {
SNOR_F_BROKEN_RESET = BIT(6),
SNOR_F_4B_OPCODES = BIT(7),
SNOR_F_HAS_4BAIT = BIT(8),
+ SNOR_F_HAS_SR_BP3 = BIT(9),
};
/**
@@ -352,6 +355,7 @@ struct flash_info;
* @dev: point to a spi device, or a spi nor controller device.
* @info: spi-nor part JDEC MFR id and other info
* @page_size: the page size of the SPI NOR
+ * @n_sectors: number of sector
* @addr_width: number of address bytes
* @erase_opcode: the opcode for erasing a sector
* @read_opcode: the read opcode
@@ -388,6 +392,7 @@ struct spi_nor {
struct device *dev;
const struct flash_info *info;
u32 page_size;
+ u16 n_sectors;
u8 addr_width;
u8 erase_opcode;
u8 read_opcode;
--
2.17.1
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[PATCH v3 3/4] mtd: spi-nor: add 4bit block protection support
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- Subject: [PATCH v3 3/4] mtd: spi-nor: add 4bit block protection support
- From: Jungseung Lee <js07.lee@xxxxxxxxxxx>
- Date: Sat, 13 Jul 2019 16:15:40 +0900
- Cms-type: 101P
- In-reply-to: <20190713071541.22090-1-js07.lee@samsung.com>
- References: <20190713071541.22090-1-js07.lee@samsung.com> <CGME20190801020520epcas1p3a9d8fc8175a5cc74be9077c2c6ee678c@epcas1p3.samsung.com>
- References:
- [PATCH v3 1/4] mtd: spi-nor: rename SR_TB to indicate the using bit
- From: Jungseung Lee
- [PATCH v3 1/4] mtd: spi-nor: rename SR_TB to indicate the using bit
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