Re: [PATCH 1/4] dt-bindings: mtd: Add YAML schemas for the generic NAND options

[Maxime Ripard <maxime.ripard@xxxxxxxxxxx>]

Hi Rob,

On Mon, Apr 01, 2019 at 08:58:49PM -0500, Rob Herring wrote:
> On Mon, Apr 1, 2019 at 4:14 PM Maxime Ripard <maxime.ripard@xxxxxxxxxxx> wrote:
> >
> > The NAND chips in MTD have a bunch of generic options that are needed in a
> > device tree. Add a YAML schemas for those.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@xxxxxxxxxxx>
> > ---
> >  Documentation/devicetree/bindings/mtd/nand-controller.yaml | 131 +++++++-
> >  1 file changed, 131 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/mtd/nand-controller.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/nand-controller.yaml b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> > new file mode 100644
> > index 000000000000..05b1afb34972
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/nand-controller.yaml
> > @@ -0,0 +1,131 @@
> > +# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NAND Chip and NAND Controller Generic Binding
> > +
> > +maintainers:
> > +  - Boris Brezillon <bbrezillon@xxxxxxxxxx>
> > +  - Miquel Raynal <miquel.raynal@xxxxxxxxxxx>
> > +  - Richard Weinberger <richard@xxxxxx>
> > +
> > +description: |
> > +  The NAND controller should be represented with its own DT node, and
> > +  all NAND chips attached to this controller should be defined as
> > +  children nodes of the NAND controller. This representation should be
> > +  enforced even for simple controllers supporting only one chip.
> > +
> > +  The ECC strength and ECC step size properties define the correction
> > +  capability of a controller. Together, they say a controller can
> > +  correct {strength} bit errors per {size} bytes.
> > +
> > +  The interpretation of these parameters is implementation-defined, so
> > +  not all implementations must support all possible
> > +  combinations. However, implementations are encouraged to further
> > +  specify the value(s) they support.
> > +
> > +properties:
> > +  $nodename:
> > +    pattern: "^nand-controller(@.*)?"
> > +
> > +  "#address-cells":
> > +    const: 1
> > +
> > +  "#size-cells":
> > +    const: 0
> > +
> > +  ranges: true
>
> 'ranges' should not be here as nand chip addresses are not translatable.

Apparently, some are. It was part of the original binding, hence why
it's there.

https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/mtd/nand.txt#L16

> > +
> > +patternProperties:
> > +  "^nand@[a-z0-9]$":
> > +    properties:
> > +      reg:
> > +        description:
> > +          Contains the native Ready/Busy IDs.
> > +
> > +      nand-ecc-mode:
> > +        allOf:
> > +          - $ref: /schemas/types.yaml#/definitions/string
> > +          - enum: [ none, soft, hw, hw_syndrome, hw_oob_first, on-die ]
> > +        description:
> > +          Operation mode of the NAND ecc mode. soft_bch is deprecated
> > +          and should be replaced by soft and nand-ecc-algo
> > +
> > +      nand-ecc-algo:
> > +        allOf:
> > +          - $ref: /schemas/types.yaml#/definitions/string
> > +          - enum: [ hamming, bch, rs ]
> > +        description:
> > +          Algorithm of NAND ECC.
> > +
> > +      nand-bus-width:
> > +        allOf:
> > +          - $ref: /schemas/types.yaml#/definitions/uint32
> > +          - enum: [ 8, 16 ]
> > +          - default: 8
> > +        description:
> > +          Bus width to the NAND chip
> > +
> > +      nand-on-flash-bbt:
> > +        $ref: /schemas/types.yaml#/definitions/flag
> > +        description:
> > +          Enable the on-flash Bad Block Table
> > +
> > +      nand-ecc-strength:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Number of bits to correct per ECC step.
>
> Is there a range we can define here? Certainly there's a minimum
> values of at least 1.

It doesn't look like there is from a quick grep. The DT seems to be in
the 4 - 32 range, but I'm not sure if it would make sense to have
something higher.

I'll let Miquel and Boris comment.

> > +
> > +      nand-ecc-step-size:
> > +        $ref: /schemas/types.yaml#/definitions/uint32
> > +        description:
> > +          Number of data bytes covered by a single ECC step.
>
> Same here.

Thanks!
Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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