Re: [PATCH 0/3] mtd: rawnand: marvell: add new layout

[Boris Brezillon <boris.brezillon@xxxxxxxxxxx>]

On Thu, 19 Jul 2018 17:23:34 +0200
Miquel Raynal <miquel.raynal@xxxxxxxxxxx> wrote:

> Hello,
> 
> This series is an attempt at supporting a new layout for Marvell NAND
> controller: NAND chips using 2kiB pages, requesting at least 8
> correctable bits per 512-byte chunks.
> 
> While this could have been trivial by the simple addition of this
> layout in the marvell_nfc_layout table as described in Marvell (not
> public) AN-379, actual testing shown a strange error. With this
> layout, one bitflip appears on the second chunk of every erased page
> when we read with BCH ECC engine activated.
> 
> It has been experimentally checked that using 64 free OOB bytes
> instead of 32 in the second chunk cancels this bitflip. However, this
> is not a viable solution as the BootROM would not find the ECC bytes
> at the right place and would declare bad any block written with this
> layout.
> 
> The solution found was to re-read in raw mode the whole page instead
> of just the ECC bytes when an ECC error occurs to check if the entire
> page is empty or not.
> 
> Also, with this layout, Bad Block Markers (BBM) are expected to be
> within the data area. Prevent any use of the BBM in this case.
> 
> The first patch reworks the ECC failure path of the BCH read function,
> the second patch adds support for the new layout with the above
> problems addressed and the last patch is just an optimization of the
> same ECC failure path for the Hamming read function.
> 
> Thanks,
> Miquèl
> 
> 
> Miquel Raynal (3):
>   mtd: rawnand: marvell: rework BCH engine failure path
>   mtd: rawnand: marvell: support 8b/512B strength for 2kiB pages layout
>   mtd: rawnand: marvell: speed-up hamming failure path

The whole series is

Reviewed-by: Boris Brezillon <boris.brezillon@xxxxxxxxxxx>

> 
>  drivers/mtd/nand/raw/marvell_nand.c | 123 +++++++++++++++++++++++-------------
>  1 file changed, 79 insertions(+), 44 deletions(-)
> 


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