[EXT] Re: [PATCH 2/2] mtd: rawnand: micron: Fix on-die ECC detection logic

[beanhuo@xxxxxxxxxx (Bean Huo (beanhuo))]

Hi, Boris
It is true. Bit7 of byte4 in READID changes after enable/disable internal ECC in case of  its default value is 0. 
Also this bit value  is volatile. After power cyling, it resets to default value. I don't know if
this condition will be changed or kept since maybe it was a specific design request from customers.
But GET Feature is still the preferred way to determine the state of ECC, we recommend using this way. 
If internal ECC is default on, we don't do anything, and if default is off, then SET feature and GET feature.
This always makes sense.

I am still digging into why this doesn't depict in datasheet and whether this will be kept in coming design.
As long I have new update, I will back to you.

>
>That's not what the board I have on my desk says. I have a
>MT29F2G08ABAEAH4, and I can tell you for sure this bit changes when I
>enable/disable on-die ECC. Do the test, and you'll see...
>
>See, that's what I'm complaining about. You keep saying things that appear to
>be untrue when when we check on real HW parts. So, either we have NANDs
>that are buggy, or you didn't check yourself.
>
>Regards,
>
>Boris