String instructions are special because in protected mode, the linear
address is always obtained via the ES segment register in operands that
use the (E)DI register. Segment override prefixes are ignored. non-
string instructions use DS as the default segment register and it can
be overridden with a segment override prefix.
This function will be used in a subsequent commmit that introduces a
function to determine the segment register to use given the instruction,
operands and segment override prefixes.
Cc: Dave Hansen <dave.hansen@xxxxxxxxxxxxxxx>
Cc: Adam Buchbinder <adam.buchbinder@xxxxxxxxx>
Cc: Colin Ian King <colin.king@xxxxxxxxxxxxx>
Cc: Lorenzo Stoakes <lstoakes@xxxxxxxxx>
Cc: Qiaowei Ren <qiaowei.ren@xxxxxxxxx>
Cc: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
Cc: Masami Hiramatsu <mhiramat@xxxxxxxxxx>
Cc: Adrian Hunter <adrian.hunter@xxxxxxxxx>
Cc: Kees Cook <keescook@xxxxxxxxxxxx>
Cc: Thomas Garnier <thgarnie@xxxxxxxxxx>
Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
Cc: Borislav Petkov <bp@xxxxxxx>
Cc: Dmitry Vyukov <dvyukov@xxxxxxxxxx>
Cc: Ravi V. Shankar <ravi.v.shankar@xxxxxxxxx>
Cc: x86@xxxxxxxxxx
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@xxxxxxxxxxxxxxx>
---
arch/x86/lib/insn-eval.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 67 insertions(+)
diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c
index 8b16761..1634762 100644
--- a/arch/x86/lib/insn-eval.c
+++ b/arch/x86/lib/insn-eval.c
@@ -16,6 +16,73 @@ enum reg_type {
REG_TYPE_BASE,
};
+enum string_instruction {
+ INSB = 0x6c,
+ INSW_INSD = 0x6d,
+ OUTSB = 0x6e,
+ OUTSW_OUTSD = 0x6f,
+ MOVSB = 0xa4,
+ MOVSW_MOVSD = 0xa5,
+ CMPSB = 0xa6,
+ CMPSW_CMPSD = 0xa7,
+ STOSB = 0xaa,
+ STOSW_STOSD = 0xab,
+ LODSB = 0xac,
+ LODSW_LODSD = 0xad,
+ SCASB = 0xae,
+ SCASW_SCASD = 0xaf,
+};
+
+/**
+ * is_string_instruction - Determine if instruction is a string instruction
+ * @insn: Instruction structure containing the opcode
+ *
+ * Return: true if the instruction, determined by the opcode, is any of the
+ * string instructions as defined in the Intel Software Development manual.
+ * False otherwise.
+ */
+static bool is_string_instruction(struct insn *insn)
+{
+ insn_get_opcode(insn);
+
+ /* all string instructions have a 1-byte opcode */
+ if (insn->opcode.nbytes != 1)
+ return false;
+
+ switch (insn->opcode.bytes[0]) {
+ case INSB:
+ /* fall through */
+ case INSW_INSD:
+ /* fall through */
+ case OUTSB:
+ /* fall through */
+ case OUTSW_OUTSD:
+ /* fall through */
+ case MOVSB:
+ /* fall through */
+ case MOVSW_MOVSD:
+ /* fall through */
+ case CMPSB:
+ /* fall through */
+ case CMPSW_CMPSD:
+ /* fall through */
+ case STOSB:
+ /* fall through */
+ case STOSW_STOSD:
+ /* fall through */
+ case LODSB:
+ /* fall through */
+ case LODSW_LODSD:
+ /* fall through */
+ case SCASB:
+ /* fall through */
+ case SCASW_SCASD:
+ return true;
+ default:
+ return false;
+ }
+}
+
static int get_reg_offset(struct insn *insn, struct pt_regs *regs,
enum reg_type type)
{
--
2.9.3
--
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