Hi Peter, On Wed, 2017-01-25 at 12:34 -0800, H. Peter Anvin wrote: > On 01/25/17 12:23, Ricardo Neri wrote: > > * SMSW returns the value with which the CR0 register is programmed in > > head_32/64.S at boot time. This is, the following bits are enabed: > > CR0.0 for Protection Enable, CR.1 for Monitor Coprocessor, CR.4 for > > Extension Type, which will always be 1 in recent processors with UMIP; > > CR.5 for Numeric Error, CR0.16 for Write Protect, CR0.18 for Alignment > > Mask. Additionally, in x86_64, CR0.31 for Paging is set. > > SMSW only returns CR0[15:0], so the reference here to CR0[31:16] seems odd. I checked again the latest version (from Dec 2016) of the Intel Software Development Manual. The documentation for SMSW states the following: SMSW r16 operand size 16, store CR0[15:0] in r16 SMSW r32 operand size 32, zero-extend CR0[31:0], and store in r32 SMSW r64 operand size 64, zero-extend CR0[63:0], and store in r64 When the operand is a memory location, yes, it only returns CR0[15:0] Also, in the tests that I ran I wrote the result of SMSW to a 64-bit register. I get 0x80050033. It seems to me that it does write as many bits as the register operand can hold. Am I missing something? Thanks and BR, Ricardo > > -hpa > > -- To unsubscribe from this list: send the line "unsubscribe linux-msdos" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
