RK3528 features two SDIO controllers and one SD/MMC controller, describe
them in devicetree. Since their sample and drive clocks are located in
the VO and VPU GRFs, corresponding syscons are added to make these
clocks available.
Signed-off-by: Yao Zi <ziyao@xxxxxxxxxxx>
---
arch/arm64/boot/dts/rockchip/rk3528.dtsi | 69 ++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
index c2eaa0c6ea90..04ca2e2b3e9b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
@@ -321,6 +321,16 @@ qos_vpu: qos@ff280400 {
reg = <0x0 0xff280400 0x0 0x20>;
};
+ vpu_grf: syscon@ff340000 {
+ compatible = "rockchip,rk3528-vpu-grf", "syscon";
+ reg = <0x0 0xff340000 0x0 0x8000>;
+ };
+
+ vo_grf: syscon@ff360000 {
+ compatible = "rockchip,rk3528-vo-grf", "syscon";
+ reg = <0x0 0xff360000 0x0 0x10000>;
+ };
+
cru: clock-controller@ff4a0000 {
compatible = "rockchip,rk3528-cru";
reg = <0x0 0xff4a0000 0x0 0x30000>;
@@ -468,6 +478,65 @@ saradc: adc@ffae0000 {
status = "disabled";
};
+ sdio0: mmc@ffc10000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc10000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDIO0>,
+ <&cru CCLK_SRC_SDIO0>,
+ <&cru SCLK_SDIO0_DRV>,
+ <&cru SCLK_SDIO0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio0_bus4>, <&sdio0_clk>, <&sdio0_cmd>;
+ resets = <&cru SRST_H_SDIO0>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdio1: mmc@ffc20000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc20000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDIO1>,
+ <&cru CCLK_SRC_SDIO1>,
+ <&cru SCLK_SDIO1_DRV>,
+ <&cru SCLK_SDIO1_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <200000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdio1_bus4>, <&sdio1_clk>, <&sdio1_cmd>;
+ resets = <&cru SRST_H_SDIO1>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ sdmmc: mmc@ffc30000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc30000 0x0 0x4000>;
+ clocks = <&cru HCLK_SDMMC0>,
+ <&cru CCLK_SRC_SDMMC0>,
+ <&cru SCLK_SDMMC_DRV>,
+ <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_bus4>, <&sdmmc_clk>, <&sdmmc_cmd>,
+ <&sdmmc_det>;
+ resets = <&cru SRST_H_SDMMC0>;
+ reset-names = "reset";
+ rockchip,default-sample-phase = <90>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rk3528-pinctrl";
rockchip,grf = <&ioc_grf>;
--
2.48.1
