On Sat, Mar 08, 2025 at 12:22:48AM +0100, Jonas Karlman wrote:
> Hi Yao Zi,
>
> On 2025-03-05 20:46, Yao Zi wrote:
> > RK3528 features two SDIO controllers and one SD/MMC controller, describe
> > them in devicetree. Since their sample and drive clocks are located in
> > the VO and VPU GRFs, corresponding syscons are added to make these
> > clocks available.
> >
> > Signed-off-by: Yao Zi <ziyao@xxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/rockchip/rk3528.dtsi | 70 ++++++++++++++++++++++++
> > 1 file changed, 70 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > index d3e2a64ff2d5..363023314e9c 100644
> > --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi
> > @@ -130,6 +130,16 @@ gic: interrupt-controller@fed01000 {
> > #interrupt-cells = <3>;
> > };
> >
> > + vpu_grf: syscon@ff340000 {
> > + compatible = "rockchip,rk3528-vpu-grf", "syscon";
> > + reg = <0x0 0xff340000 0x0 0x8000>;
> > + };
> > +
> > + vo_grf: syscon@ff360000 {
> > + compatible = "rockchip,rk3528-vo-grf", "syscon";
> > + reg = <0x0 0xff360000 0x0 0x10000>;
> > + };
> > +
> > cru: clock-controller@ff4a0000 {
> > compatible = "rockchip,rk3528-cru";
> > reg = <0x0 0xff4a0000 0x0 0x30000>;
> > @@ -274,6 +284,66 @@ saradc: adc@ffae0000 {
> > resets = <&cru SRST_P_SARADC>;
> > reset-names = "saradc-apb";
> > #io-channel-cells = <1>;
> > + };
>
> Look like this patch accidentally drops status = "disabled" from the
> adc@ffae0000 node.
It's a mistake during rebasing, I'll fix it in v3.
> Regards,
> Jonas
Thanks,
Yao Zi
