> -----Original Message----- > From: Josua Mayer <josua@xxxxxxxxxxxxx> > Sent: 2024年11月1日 19:42 > To: Adrian Hunter <adrian.hunter@xxxxxxxxx>; Bough Chen > <haibo.chen@xxxxxxx>; Ulf Hansson <ulf.hansson@xxxxxxxxxx>; Shawn Guo > <shawnguo@xxxxxxxxxx>; Sascha Hauer <s.hauer@xxxxxxxxxxxxxx>; > Pengutronix Kernel Team <kernel@xxxxxxxxxxxxxx>; Fabio Estevam > <festevam@xxxxxxxxx> > Cc: Mikhail Anikin <mikhail.anikin@xxxxxxxxxxxxx>; Jon Nettleton > <jon@xxxxxxxxxxxxx>; yazan.shhady <yazan.shhady@xxxxxxxxxxxxx>; Rabeeh > Khoury <rabeeh@xxxxxxxxxxxxx>; imx@xxxxxxxxxxxxxxx; > linux-mmc@xxxxxxxxxxxxxxx; dl-S32 <S32@xxxxxxx>; > linux-arm-kernel@xxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; Josua > Mayer <josua@xxxxxxxxxxxxx> > Subject: [PATCH v3 2/2] mmc: host: sdhci-esdhc-imx: update esdhc sysctl dtocv > bitmask > > NXP ESDHC supports setting data timeout using uSDHCx_SYS_CTRL register > DTOCV bits (bits 16-19). > Currently the driver accesses those bits by 32-bit write using > SDHCI_TIMEOUT_CONTROL (0x2E) defined in drivers/mmc/host/sdhci.h. > This is offset by two bytes relative to uSDHCx_SYS_CTRL (0x2C). > The driver also defines ESDHC_SYS_CTRL_DTOCV_MASK as first 4 bits, which is > correct relative to SDHCI_TIMEOUT_CONTROL but not relative to > uSDHCx_SYS_CTRL. The definition carrying control register in its name is > therefore inconsistent. > > Update the bitmask definition for bits 16-19 to be correct relative to control > register base. > Update the esdhc_set_timeout function to set timeout value at control register > base, not timeout offset. > > This solves a purely cosmetic problem. Reviewed-by: Haibo Chen <haibo.chen@xxxxxxx> Best Regards Haibo Chen > > Signed-off-by: Josua Mayer <josua@xxxxxxxxxxxxx> > --- > drivers/mmc/host/sdhci-esdhc-imx.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c > b/drivers/mmc/host/sdhci-esdhc-imx.c > index > f106e291c276d0c8063e9ac59a126acf5e9e239e..cda3cc4cc22cfa214369f40f09 > 7ca50937898604 100644 > --- a/drivers/mmc/host/sdhci-esdhc-imx.c > +++ b/drivers/mmc/host/sdhci-esdhc-imx.c > @@ -30,7 +30,7 @@ > #include "sdhci-esdhc.h" > #include "cqhci.h" > > -#define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f > +#define ESDHC_SYS_CTRL_DTOCV_MASK GENMASK(19, 16) > #define ESDHC_SYS_CTRL_IPP_RST_N BIT(23) > #define ESDHC_CTRL_D3CD 0x08 > #define ESDHC_BURST_LEN_EN_INCR (1 << 27) > @@ -1386,8 +1386,8 @@ static void esdhc_set_timeout(struct sdhci_host > *host, struct mmc_command *cmd) > > /* use maximum timeout counter */ > esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, > - esdhc_is_usdhc(imx_data) ? 0xF : 0xE, > - SDHCI_TIMEOUT_CONTROL); > + esdhc_is_usdhc(imx_data) ? 0xF0000 : 0xE0000, > + ESDHC_SYSTEM_CONTROL); > } > > static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) > > -- > 2.43.0
