On 7/10/24 12:54, Paul Alvin wrote:
> Add hw_reset callback to support emmc hardware reset, this callback get
> called from the mmc core only when "cap-mmc-hw-reset" property is
> defined in the DT.
>
> Signed-off-by: Paul Alvin <alvin.paulp@xxxxxxx>
Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
> ---
>
> Changes in v2:
> - Updated the CC list
>
> drivers/mmc/host/sdhci-of-arasan.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c
> index 5edd024347bd..0cb05bdec34d 100644
> --- a/drivers/mmc/host/sdhci-of-arasan.c
> +++ b/drivers/mmc/host/sdhci-of-arasan.c
> @@ -76,6 +76,8 @@
> #define FREQSEL_225M_200M 0x7
> #define PHY_DLL_TIMEOUT_MS 100
>
> +#define SDHCI_HW_RST_EN BIT(4)
> +
> /* Default settings for ZynqMP Clock Phases */
> #define ZYNQMP_ICLK_PHASE {0, 63, 63, 0, 63, 0, 0, 183, 54, 0, 0}
> #define ZYNQMP_OCLK_PHASE {0, 72, 60, 0, 60, 72, 135, 48, 72, 135, 0}
> @@ -475,6 +477,21 @@ static void sdhci_arasan_reset(struct sdhci_host *host, u8 mask)
> }
> }
>
> +static void sdhci_arasan_hw_reset(struct sdhci_host *host)
> +{
> + u8 reg;
> +
> + reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
> + reg |= SDHCI_HW_RST_EN;
> + sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
> + /* As per eMMC spec, minimum 1us is required but give it 2us for good measure */
> + usleep_range(2, 5);
> + reg &= ~SDHCI_HW_RST_EN;
> + sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
> + /* As per eMMC spec, minimum 200us is required but give it 300us for good measure */
> + usleep_range(300, 500);
> +}
> +
> static int sdhci_arasan_voltage_switch(struct mmc_host *mmc,
> struct mmc_ios *ios)
> {
> @@ -505,6 +522,7 @@ static const struct sdhci_ops sdhci_arasan_ops = {
> .reset = sdhci_arasan_reset,
> .set_uhs_signaling = sdhci_set_uhs_signaling,
> .set_power = sdhci_set_power_and_bus_voltage,
> + .hw_reset = sdhci_arasan_hw_reset,
> };
>
> static u32 sdhci_arasan_cqhci_irq(struct sdhci_host *host, u32 intmask)
