On 2024/6/21 0:15, Jisheng Zhang wrote:
On Tue, Jun 18, 2024 at 04:38:30PM +0800, Chen Wang wrote:
From: Chen Wang <unicorn_wang@xxxxxxxxxxx>
SG2042 use Synopsys dwcnshc IP for SD/eMMC controllers.
SG2042 defines 3 clocks for SD/eMMC controllers.
- AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc)
and blck(Core Base Clock in DWC_mshc), these 3 clocks share one
source, so reuse existing "core".
No, this seems not correct. This should be the "bus" clk, and your above
sentence "aclk/hclk(Bus interface clocks in DWC_mshc)" implies this clk is
for bus
- 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse
existing "timer" which was added for rockchip specified.
- EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), add new "card".
I think this is "core" clk, no? Plz check which internal clks' clock
source is the so called EMMC_100M/SD_100M.
hi, Jisheng,
Just want to double-confirm, corresponding to the definition of clock in
the dwc-mshc specification, what's the "core" clock in the
snps,dwcmshc-sdhci.yaml?
I get following clock definitions in user-guide of dwc-mshc
specification, in section 1.8 "Speed and Clock Requirements"
- 1.8.1 Bus Interface Clocks，which are aclk and m_hclk/hclk
- 1.8.2 Timer Clocks，which are tmclk，cqetmclk
- 1.8.3 Card Clocks， whichi is cclk
- 1.8.4 Core Base Clock，which is bclk
I used to think "core" is "Core Base Clock".
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