From: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> The controller's minimum possible bus clock is 1/30 the rate of the input clock. Naively set the minimum bus clock speed the controller is capable of during probe, assuming that the rate will never reduce further. Signed-off-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx> --- drivers/spi/spi-microchip-core-qspi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microchip-core-qspi.c index 1b23a38c155c..a549911b2f66 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -763,6 +763,7 @@ static int mchp_coreqspi_probe(struct platform_device *pdev) ctlr->transfer_one_message = mchp_coreqspi_transfer_one_message; ctlr->num_chipselect = 2; ctlr->use_gpio_descriptors = true; + ctlr->min_speed_hz = clk_get_rate(qspi->clk) / 30; ret = devm_spi_register_controller(&pdev->dev, ctlr); if (ret) -- 2.43.0
