On 20/03/2024 10:36, Maxim Kiselev wrote: > Subject: [PATCH v7 0/2] mmc: sdhci-of-dwcmshc: Add CQE support > > Hi Sergey, Adrian! > > First of all I want to thank Sergey for supporting the CQE feature > on the DWC MSHC controller. > > I tested this series on the LicheePi 4A board (TH1520 SoC). > It has the DWC MSHC IP too and according to the T-Head datasheet > it also supports the CQE feature. > >> Supports Command Queuing Engine (CQE) and compliant with eMMC CQ HCI. > > So, to enable CQE on LicheePi 4A need to set a prop in DT > and add a IRQ handler to th1520_ops: >> .irq = dwcmshc_cqe_irq_handler, > > And the CQE will work for th1520 SoC too. > > But, when I enabled the CQE, I was faced with a strange effect. > > The fio benchmark shows that emmc works ~2.5 slower with enabled CQE. > 219MB/s w/o CQE vs 87.4MB/s w/ CQE. I'll put logs below. > > I would be very appreciative if you could point me where to look for > the bottleneck. > > Without CQE: I would also suspect some bus issues here, either read out ios or ext_csd after enabling CQE, it could be helpful. OTOH the CQE could just be limiting the frequency, which you wouldn't be able to see without a scope. Does the TRM say anything about that? Are you limited to <100MB/s with CQE for HS400(non-ES) and HS200, too? What about sequential reads but smaller bs? like 256K sequential? FWIW your fio call should be on par with non-CQE performance-wise at best, as you just have one IO in-flight, i.e. no CQE performance improvement possible, see your warning: > both iodepth >= 1 and synchronous I/O engine are selected, queue > depth will be capped at 1 Kind Regards, Christian
