For DDR52 timing, DLL is enabled but tuning is not carried
out, therefore the ITAPDLY value in PHY CTRL 4 register is
not correct. Fix this by writing ITAPDLY after enabling DLL.
Fixes: a161c45f2979 ("mmc: sdhci_am654: Enable DLL only for some speed modes")
Signed-off-by: Judith Mendez <jm@xxxxxx>
Reviewed-by: Andrew Davis <afd@xxxxxx>
Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
---
Changelog:
v3->v4:
- Add acked-by
---
drivers/mmc/host/sdhci_am654.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c
index fb802bf7ad1c..d079b25ef4c9 100644
--- a/drivers/mmc/host/sdhci_am654.c
+++ b/drivers/mmc/host/sdhci_am654.c
@@ -300,6 +300,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock)
if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) {
sdhci_am654_setup_dll(host, clock);
sdhci_am654->dll_enable = true;
+ sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing]);
} else {
sdhci_am654_setup_delay_chain(sdhci_am654, timing);
}
--
2.43.2
