Add DT bindings documentation for Cadence SD/eMMC host controller (Version 6) driver. Signed-off-by: Alex Soo <yuklin.soo@xxxxxxxxxxxxxxxx> --- .../devicetree/bindings/mmc/cdns,sd6hci.yaml | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 Documentation/devicetree/bindings/mmc/cdns,sd6hci.yaml diff --git a/Documentation/devicetree/bindings/mmc/cdns,sd6hci.yaml b/Documentation/devicetree/bindings/mmc/cdns,sd6hci.yaml new file mode 100644 index 000000000000..97e28d720c7b --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/cdns,sd6hci.yaml @@ -0,0 +1,65 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/cdns,sd6hci.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence SD/SDIO/eMMC Host Controller Version 6.0 (SD6HC) + +maintainers: + - Alex Soo <yuklin.soo@xxxxxxxxxxxxxxxx> + +allOf: + - $ref: mmc-controller.yaml + +properties: + compatible: + items: + - enum: + - starfive,jh8100-sd6hc + - const: cdns,sd6hc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + items: + - const: main + - const: sdmclk + + clocks: + items: + - description: main clock gate which controls the gating of all clock signals to SDHCI + controller + - description: the SD master clock signal + + resets: + items: + - description: reset phandle which controls the assert/deassert of all reset lines to + SDHCI controller + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - resets + +unevaluatedProperties: false + +examples: + - | + emmc: mmc@1f110000 { + compatible = "starfive,jh8100-sd6hc", "cdns,sd6hc"; + reg = <0x1f110000 0x10000>; + interrupts = <174>; + clock-names = "main", "sdmclk"; + clocks = <&aoncrg 62>, + <&aoncrg 43>; + resets = <&aoncrg 9>; + bus-width = <8>; + }; -- 2.25.1
