On Fri, 3 Nov 2023 at 11:13, Victor Shih <victorshihgli@xxxxxxxxx> wrote: > > Hi, Ulf > > Please help review this patch and give me some advice. > I look forward to your reply. > > Thanks, Victor Shih I don't have in-depth knowledge of how to properly solve this for pci, so I am relying on Kai and others to help review. > > On Wed, Oct 18, 2023 at 6:33 PM Victor Shih <victorshihgli@xxxxxxxxx> wrote: > > > > From: Victor Shih <victor.shih@xxxxxxxxxxxxxxxxxxx> > > > > Due to a flaw in the hardware design, the GL975x replay timer frequently > > times out when ASPM is enabled. As a result, the warning messages that will > > often appear in the system log when the system accesses the GL975x > > PCI config. Therefore, the replay timer timeout must be masked. > > > > Signed-off-by: Victor Shih <victor.shih@xxxxxxxxxxxxxxxxxxx> The code looks good to me, but let's allow Kai to get some time to come back to this before I apply it. Kind regards Uffe > > --- > > > > Updates in V2: > > - Modify the commit message. > > > > --- > > > > drivers/mmc/host/sdhci-pci-gli.c | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c > > index d83261e857a5..d8a991b349a8 100644 > > --- a/drivers/mmc/host/sdhci-pci-gli.c > > +++ b/drivers/mmc/host/sdhci-pci-gli.c > > @@ -28,6 +28,9 @@ > > #define PCI_GLI_9750_PM_CTRL 0xFC > > #define PCI_GLI_9750_PM_STATE GENMASK(1, 0) > > > > +#define PCI_GLI_9750_CORRERR_MASK 0x214 > > +#define PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12) > > + > > #define SDHCI_GLI_9750_CFG2 0x848 > > #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) > > #define GLI_9750_CFG2_L1DLY_VALUE 0x1F > > @@ -152,6 +155,9 @@ > > #define PCI_GLI_9755_PM_CTRL 0xFC > > #define PCI_GLI_9755_PM_STATE GENMASK(1, 0) > > > > +#define PCI_GLI_9755_CORRERR_MASK 0x214 > > +#define PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT BIT(12) > > + > > #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 > > #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) > > > > @@ -561,6 +567,11 @@ static void gl9750_hw_setting(struct sdhci_host *host) > > value &= ~PCI_GLI_9750_PM_STATE; > > pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value); > > > > + /* mask the replay timer timeout of AER */ > > + pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value); > > + value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT; > > + pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value); > > + > > gl9750_wt_off(host); > > } > > > > @@ -770,6 +781,11 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot) > > value &= ~PCI_GLI_9755_PM_STATE; > > pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value); > > > > + /* mask the replay timer timeout of AER */ > > + pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value); > > + value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT; > > + pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value); > > + > > gl9755_wt_off(pdev); > > } > > > > -- > > 2.25.1 > >
