Hi Claudiu,
On Mon, Sep 18, 2023 at 9:50 AM claudiu beznea <claudiu.beznea@xxxxxxxxx> wrote:
> On 15.09.2023 15:52, Geert Uytterhoeven wrote:
> > On Tue, Sep 12, 2023 at 6:53 AM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> >> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> >>
> >> Add minimal clock and reset support for RZ/G3S SoC to be able to boot
> >> Linux from SD Card/eMMC. This includes necessary core clocks for booting
> >> and GIC, SCIF, GPIO, SD0 mod clocks and resets.
> >>
> >> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
> >
> > Thanks for your patch!
> >
>
> [ ... ]
>
> >> + CLK_PLL3_DIV2_4,
> >> + CLK_PLL3_DIV2_8,
> >> + CLK_PLL3_DIV6,
> >> + CLK_PLL4,
> >> + CLK_PLL6,
> >> + CLK_PLL6_DIV2,
> >> + CLK_SEL_SDHI0,
> >> + CLK_SEL_PLL4,
> >> + CLK_P1_DIV2,
> >> + CLK_P3_DIV2,
> >
> > Do you need CLK_P1_DIV2 and CLK_P3_DIV2?
> > I don't see them in Figure 7.3 ("Clock System Diagram (2)").
>
> P1_DIV2 is clock source for MHU_PCLK or OTFDE_DDR_PCLK.
> P3_DIV2 is clock source for DMAC_PCLK, OTFDE_SPI_PCLK.
> These are expressed in clock list document
> (RZG3S_clock_list_r1.00_20230602.xlsx).
>
> It is true the functionality could be preserved even w/o these 2 clocks but
> I kept them here as I saw them as core clocks even though they are not
> present in the Clock System Diagram from HW manual.
I don't think you can, as the module clock abstraction does not support
specifying a divider. Hence you do need an internal core clock between
P1 and the module clock, to take care of the divider.
> With these, would you prefer to keep these clocks or just remove them?
Yes, as I expect that at least the DMAC_PCLK will be added, eventually.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
