On 17/07/23 15:51, Piyush Malgujar wrote:
> From: Jayanthi Annadurai <jannadurai@xxxxxxxxxxx>
>
> Add support of CONFIG_MMC_SDHCI_IO_ACCESSORS to allow Marvell
> SoC ops for SD6 controller to overwrite the SDHCI IO memory
> accessors.
>
> Signed-off-by: Jayanthi Annadurai <jannadurai@xxxxxxxxxxx>
> Signed-off-by: Piyush Malgujar <pmalgujar@xxxxxxxxxxx>
> ---
> drivers/mmc/host/sdhci-cadence.c | 59 ++++++++++++++++++++++++++++++++
> 1 file changed, 59 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c
> index 8bcf585185053b0afaff2625d62316cec1824fa3..f1e597219c603f3921439cedb22dcb2884abe68d 100644
> --- a/drivers/mmc/host/sdhci-cadence.c
> +++ b/drivers/mmc/host/sdhci-cadence.c
> @@ -448,6 +448,59 @@ static u32 read_dqs_cmd_delay, clk_wrdqs_delay, clk_wr_delay, read_dqs_delay;
>
> static u32 sdhci_cdns_sd6_get_mode(struct sdhci_host *host, unsigned int timing);
>
> +static u32 sdhci_cdns_sd6_readl(struct sdhci_host *host, int reg)
> +{
> + return readl(host->ioaddr + reg);
> +}
Doesn't need to be implemented if it is the same as the
default behaviour
> +
> +static void sdhci_cdns_sd6_writel(struct sdhci_host *host, u32 val, int reg)
> +{
> + writel(val, host->ioaddr + reg);
> +}
Doesn't need to be implemented if it is the same as the
default behaviour
> +
> +static u16 sdhci_cdns_sd6_readw(struct sdhci_host *host, int reg)
> +{
> + u32 val, regoff;
> +
> + regoff = reg & ~3;
> +
> + val = readl(host->ioaddr + regoff);
> + if ((reg & 0x3) == 0)
> + return (val & 0xFFFF);
> + else
> + return ((val >> 16) & 0xFFFF);
> +}
You can use upper_16_bits() etc e.g.
static u16 sdhci_cdns_sd6_readw(struct sdhci_host *host, int reg)
{
u32 val = readl(host->ioaddr + (reg & ~3));
return reg & 0x3 ? upper_16_bits(val) : lower_16_bits(val);
}
> +
> +static void sdhci_cdns_sd6_writew(struct sdhci_host *host, u16 val, int reg)
> +{
> + writew(val, host->ioaddr + reg);
> +}
Doesn't need to be implemented if it is the same as the
default behaviour
> +
> +static u8 sdhci_cdns_sd6_readb(struct sdhci_host *host, int reg)
> +{
> + u32 val, regoff;
> +
> + regoff = reg & ~3;
> +
> + val = readl(host->ioaddr + regoff);
> + switch (reg & 3) {
> + case 0:
> + return (val & 0xFF);
> + case 1:
> + return ((val >> 8) & 0xFF);
> + case 2:
> + return ((val >> 16) & 0xFF);
> + case 3:
> + return ((val >> 24) & 0xFF);
> + }
> + return 0;
> +}
Probably could just be:
static u8 sdhci_cdns_sd6_readb(struct sdhci_host *host, int reg)
{
u32 val = readl(host->ioaddr + (reg & ~3));
return val >> (8 * (reg & 3)));
}
> +
> +static void sdhci_cdns_sd6_writeb(struct sdhci_host *host, u8 val, int reg)
> +{
> + writeb(val, host->ioaddr + reg);
> +}
Doesn't need to be implemented if it is the same as the
default behaviour
> +
> static int sdhci_cdns_sd6_phy_lock_dll(struct sdhci_cdns_sd6_phy *phy)
> {
> u32 delay_element = phy->d.delay_element_org;
> @@ -1666,6 +1719,12 @@ static const struct sdhci_ops sdhci_cdns_sd4_ops = {
> };
>
> static const struct sdhci_ops sdhci_cdns_sd6_ops = {
> + .read_l = sdhci_cdns_sd6_readl,
> + .write_l = sdhci_cdns_sd6_writel,
> + .read_w = sdhci_cdns_sd6_readw,
> + .write_w = sdhci_cdns_sd6_writew,
> + .read_b = sdhci_cdns_sd6_readb,
> + .write_b = sdhci_cdns_sd6_writeb,
> .get_max_clock = sdhci_cdns_get_max_clock,
> .set_clock = sdhci_cdns_sd6_set_clock,
> .get_timeout_clock = sdhci_cdns_get_timeout_clock,
