On 24/03/2023 08:36, Sai Krishna Potthuri wrote: > Add Xilinx Versal Net compatible to support eMMC 5.1 PHY. > > Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@xxxxxxx> > --- > Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml > index 8296c34cfa00..cf44a4b988a7 100644 > --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml > +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml > @@ -27,6 +27,7 @@ allOf: > enum: > - xlnx,zynqmp-8.9a > - xlnx,versal-8.9a > + - xlnx,versal-net-5.1-emmc v5.1 is eMMC standard or Versal block version? If the first, it's not suitable for compatibles. Also, what's the difference from xlnx,versal-8.9a? > then: > properties: > clock-output-names: > @@ -62,6 +63,11 @@ properties: > description: > For this device it is strongly suggested to include > clock-output-names and '#clock-cells'. > + - items: > + - const: xlnx,versal-net-5.1-emmc # Versal Net eMMC PHY > + description: Best regards, Krzysztof
