On 12/03/2023 18:58, Sergey Lisov wrote: > DesignWare MMC cores have a configurable data bus width of either 16, 32, or 64 > bytes. It is possible, and some vendors actually do it, to ship a DW MMC core > configured for 32-bit data bus within a 64-bit SoC. In this case the kernel > will attempt 64-bit (readq) accesses to certain 64-bit MMIO registers, while > the core will expect pairs of 32-bit accesses. > > It seems that currently the only register for which the kernel performs 64-bit > accesses is the FIFO. The symptom is that the DW MMC core never receives a read > on the second half of the register, does not register the datum as being read, > and thus not advancing its internal FIFO pointer, breaking further reads. It > also seems that this FIFO is only used for small (less than 16 bytes) > transfers, which probably means that only some SDIO cards are affected. > > Changelog: > > v5: > - rename "samsung,exynos78xx-dw-mshc" to "samsung,exynos7885-dw-mshc" > - rename "samsung,exynos78xx-dw-mshc" to "samsung,exynos7885-dw-mshc" So this is fifth version today? You need to wait before resending, to gather other comments. Also, something is wrong with your mailing. Threading is gone and all patches arrive twice with different Message IDs. Best regards, Krzysztof
