On 12/03/2023 17:59, Sergey Lisov wrote:
> Some Samsung Exynos boards using the arm64 architecture have DW MMC
> controllers configured for a 32-bit data bus but a 64-bit FIFO. On these
> systems the 64-bit FIFO registers must be accessed in two 32-bit halves.
> ---
> drivers/mmc/host/dw_mmc-exynos.c | 41 ++++++++++-
> drivers/mmc/host/dw_mmc.c | 122 ++++++++++++++++++++++++++++++-
> drivers/mmc/host/dw_mmc.h | 2 +
> 3 files changed, 162 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c
> index 9f20ac524..768774f22 100644
> --- a/drivers/mmc/host/dw_mmc-exynos.c
> +++ b/drivers/mmc/host/dw_mmc-exynos.c
> @@ -28,6 +28,8 @@ enum dw_mci_exynos_type {
> DW_MCI_TYPE_EXYNOS5420_SMU,
> DW_MCI_TYPE_EXYNOS7,
> DW_MCI_TYPE_EXYNOS7_SMU,
> + DW_MCI_TYPE_EXYNOS78XX,
> + DW_MCI_TYPE_EXYNOS78XX_SMU,
> DW_MCI_TYPE_ARTPEC8,
> };
>
> @@ -70,6 +72,12 @@ static struct dw_mci_exynos_compatible {
> }, {
> .compatible = "samsung,exynos7-dw-mshc-smu",
> .ctrl_type = DW_MCI_TYPE_EXYNOS7_SMU,
> + }, {
> + .compatible = "samsung,exynos78xx-dw-mshc",
> + .ctrl_type = DW_MCI_TYPE_EXYNOS78XX,
> + }, {
> + .compatible = "samsung,exynos78xx-dw-mshc-smu",
> + .ctrl_type = DW_MCI_TYPE_EXYNOS78XX_SMU,
> }, {
> .compatible = "axis,artpec8-dw-mshc",
> .ctrl_type = DW_MCI_TYPE_ARTPEC8,
> @@ -86,6 +94,8 @@ static inline u8 dw_mci_exynos_get_ciu_div(struct dw_mci *host)
> return EXYNOS4210_FIXED_CIU_CLK_DIV;
> else if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 ||
> priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU ||
> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX ||
> + priv->ctrl_type == DW_MCI_TYPE_EXYNOS78XX_SMU ||
> priv->ctrl_type == DW_MCI_TYPE_ARTPEC8)
This is getting look like a spaghetti code. I think this needs
quirks/flags, except of types. Or this ifs all over should be made a bit
smarter as all of these are pretty close to compatible.
Best regards,
Krzysztof
