On Tue, Feb 28, 2023 at 11:37:20AM +0100, Krzysztof Kozlowski wrote: > On 28/02/2023 10:05, William Qiu wrote: > > On 2023/2/28 6:29, Rob Herring wrote: > >> On Tue, Feb 21, 2023 at 10:44:02AM +0800, William Qiu wrote: > >>> On 2023/2/21 7:43, Rob Herring wrote: > >>>> On Wed, Feb 15, 2023 at 07:32:49PM +0800, William Qiu wrote: > >>>>> Add documentation to describe StarFive System Controller Registers. > >>>>> > >>>>> Signed-off-by: William Qiu <william.qiu@xxxxxxxxxxxxxxxx> > >>>>> --- > >>>>> .../bindings/soc/starfive/jh7110-syscon.yaml | 51 +++++++++++++++++++ > >>>>> MAINTAINERS | 5 ++ > >>>>> 2 files changed, 56 insertions(+) > >>>>> create mode 100644 Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml > >>>>> > >>>>> diff --git a/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml > >>>>> new file mode 100644 > >>>>> index 000000000000..fa4d8522a454 > >>>>> --- /dev/null > >>>>> +++ b/Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml > >>>>> @@ -0,0 +1,51 @@ > >>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > >>>>> +%YAML 1.2 > >>>>> +--- > >>>>> +$id: http://devicetree.org/schemas/soc/starfive/jh7110-syscon.yaml# > >>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >>>>> + > >>>>> +title: StarFive JH7110 SoC system controller > >>>>> + > >>>>> +maintainers: > >>>>> + - William Qiu <william.qiu@xxxxxxxxxxxxxxxx> > >>>>> + > >>>>> +description: | > >>>>> + The StarFive JH7110 SoC system controller provides register information such > >>>>> + as offset, mask and shift to configure related modules such as MMC and PCIe. > >>>>> + > >>>>> +properties: > >>>>> + compatible: > >>>>> + items: > >>>>> + - enum: > >>>>> + - starfive,jh7110-stg-syscon > >>>>> + - starfive,jh7110-sys-syscon > >>>>> + - starfive,jh7110-aon-syscon > >>>> > >>>> Is 'syscon' really part of what the blocks are called? Is just 'stg', > >>>> 'sys' and 'aon' not unique enough? > >>> In StarFive SoC, we do have syscrg/aoncrg/stgcrg, which is uesd to be the clock > >>> controller, so 'syscon' is added to avoid confusion. > >> > >> You've only added to my confusion. 'syscrg' and 'sys-syscon' are 2 > >> different h/w blocks and unrelated to each other? Or 'syscrg' is the > >> clock portion of 'sys-syscon'? In that case, 'syscrg' should be a child > >> of 'sys-syscon' or possibly just all one node. Please provide details on > >> the entire h/w block so we can provide better input on the bindings. > > It's my description that's problematic.'syscon' here refers to the hardware module > > inside our JH7110, which is different from the syscon interface in linux. The syscon > > I added now uses the syscon interface of linux to read and write the syscon register > > in our JH7110. So we decided to name it that way. > > You didn't really answer Rob's questions. > > Also, syscon is Linux term, so are you sure hardware module is called > like this? Hardware engineers took pure Linux name and used it? Their TRM uses the term SYSCON for these, yes. Eg: "The JH7110 system provides the following STG SYSCON control registers which provides [sic] clock and reset signals to interfaces..." In fact, the TRM I have describes the following system control register blocks: SYS CRG STG CRG AON CRG SYS SYSCON STG SYSCON AON SYSCON SYS IOMUX CFG AON IOMUX CFG My understanding is that the first 3 (the CRG ones) are concerned with clocks and resets & the second 3 contain "random" configuration options, such as their QSPI IP's configuration options, GPIO voltage settings etc. Each of these has a separate, 0x1000 aligned, block in the memory map. Cheers, Conor.
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