Hi Rob, On Wednesday, November 16, 2022 2:30 PM, Rob Herring wrote: >On Wed, Nov 16, 2022 at 11:39:40AM -0800, Brad Larson wrote: >> Add support for the AMD Pensando Elba SoC System Resource chip >> using the SPI interface. > > Please resend the whole series properly threaded. Series sent as v9 >> +description: | >> + AMD Pensando Elba SoC Resource Controller functions are >> + accessed with four chip-selects. Reset control is on CS0. > > One device with 4 chip-selects? Then I'd expect 'reg = <0 1 2 3>;' > > Hard to say more because I don't have the whole thread nor remember what > exactly we discussed before. That was 100s of bindings ago... This has been changed to one device and four chip selects. This binding error is occuring for snps,dw-apb-ssi.yaml using reg for the chip selects. Any guidance on how to fix? $ make ARCH=arm64 dtbs_check DT_SCHEMA_FILES=Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml LINT Documentation/devicetree/bindings CHKDT Documentation/devicetree/bindings/processed-schema.json SCHEMA Documentation/devicetree/bindings/processed-schema.json DTC_CHK arch/arm64/boot/dts/amd/elba-asic.dtb /home/brad/linux.v10/arch/arm64/boot/dts/amd/elba-asic.dtb: spi@2800: system-controller@0:reg: [[0], [1], [2], [3]] is too long From schema: /home/brad/linux.v10/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml Binding: --- /dev/null +++ b/Documentation/devicetree/bindings/spi/amd,pensando-sr.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/amd,pensando-sr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: AMD Pensando SoC Resource Controller + +description: | + AMD Pensando SoC Resource Controller is a set of control/status + registers accessed on four chip-selects. This device is present + in all Pensando SoC based designs. + + CS0 is a set of miscellaneous control/status registers to + include reset control. CS1/CS2 are for I2C peripherals. + CS3 is to access resource controller internal storage. + +maintainers: + - Brad Larson <blarson@xxxxxxx> + +properties: + compatible: + const: amd,pensando-sr + + reg: + maxItems: 4 + minimum: 0 + maximum: 3 + description: + Device chip select number + + '#reset-cells': + const: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - spi-max-frequency + - '#reset-cells' + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + num-cs = <4>; + + system-controller@0 { + compatible = "amd,pensando-sr"; + reg = <0 1 2 3>; + spi-max-frequency = <12000000>; + interrupt-parent = <&porta>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + #reset-cells = <1>; + }; + }; + +... DT node, single device and using reg for four chip-selects &spi0 { #address-cells = <1>; #size-cells = <0>; num-cs = <4>; cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>, <&porta 7 GPIO_ACTIVE_LOW>; status = "okay"; rstc: system-controller@0 { compatible = "amd,pensando-sr"; reg = <0 1 2 3>; spi-max-frequency = <12000000>; interrupt-parent = <&porta>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; #reset-cells = <1>; }; }; Regards, Brad
