On 19/09/2022 20:13, Dinh Nguyen wrote:
> The sdmmc controller's CIU(Card Interface Unit) clock's phase can be
> adjusted through the register in the system manager. Add the binding
> "altr,sysmgr-syscon" to the SDMMC node for the driver to access the
> system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to
> designate the smpsel and drvsel properties for the CIU clock.
>
> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 +
> arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 +
> arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 +
> arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 1 +
> arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 1 +
> 5 files changed, 5 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index 14c220d87807..a5d08920ac81 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -309,6 +309,7 @@ mmc: mmc@ff808000 {
> <&clkmgr STRATIX10_SDMMC_CLK>;
> clock-names = "biu", "ciu";
> iommus = <&smmu 5>;
> + altr,sysmgr-syscon = <&sysmgr 0x28 0>;
Missing bindings change.
Best regards,
Krzysztof
