> Am 14.07.2022 um 18:44 schrieb Christian Loehle <CLoehle@xxxxxxxxxxxxxx>: > > I only briefly skimmed the discussion, but does this mean that a soft-reset (CMD0) of a UHS (post-voltage-switch) will not work? > (As the card/spec requires a power-cycle by the host which will not come, right?) > Can you try this real quick? I can give you a mmc-utils snippet if you have trouble issuing one. > If that does indeed not work I think the general approach is to disable uhs in the dts or at least document that. > Regards, > Christian I tried disabling UHS in the DTS, but that would still cause mmc detection issues. "rmmod dw_mmc_rockchip" followed by "modprobe dw_mmc_rockchip" still detects the card: > [ 4481.141764] mmc1: card 0001 removed > [ 4488.133398] dwmmc_rockchip fe320000.mmc: IDMAC supports 32-bit address mode. > [ 4488.133462] dwmmc_rockchip fe320000.mmc: Using internal DMA controller. > [ 4488.133484] dwmmc_rockchip fe320000.mmc: Version ID is 270a > [ 4488.133541] dwmmc_rockchip fe320000.mmc: DW MMC controller at irq 32,32 bit host data width,256 deep fifo > [ 4488.134320] dwmmc_rockchip fe320000.mmc: Got CD GPIO > [ 4488.147329] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) > [ 4488.218364] mmc_host mmc1: Bus speed (slot 0) = 148500000Hz (slot req 150000000Hz, actual 148500000HZ div = 0) > [ 4488.678181] dwmmc_rockchip fe320000.mmc: Successfully tuned phase to 214 > [ 4488.678239] mmc1: new ultra high speed SDR104 SDHC card at address 0001 > [ 4488.680315] mmcblk1: mmc1:0001 ASTC 14.6 GiB > [ 4488.684871] mmcblk1: p1 p2 Ejecting/re-inserting the card also works: > [ 4607.521119] mmc1: card 0001 removed > [ 4608.517343] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) > [ 4608.632987] mmc_host mmc1: Bus speed (slot 0) = 148500000Hz (slot req 150000000Hz, actual 148500000HZ div = 0) > [ 4609.065445] dwmmc_rockchip fe320000.mmc: Successfully tuned phase to 213 > [ 4609.065535] mmc1: new ultra high speed SDR104 SDHC card at address 0001 > [ 4609.067942] mmcblk1: mmc1:0001 ASTC 14.6 GiB > [ 4609.073521] mmcblk1: p1 p2 and so is changing the clock back and forth: > echo 400000 > /sys/kernel/debug/mmc1/clock; echo 150000000 > kernel/debug/mmc1/clock; fdisk -l /dev/mmcblk1 > [ 4817.829078] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) > [ 4820.063457] mmc_host mmc1: Bus speed (slot 0) = 148500000Hz (slot req 150000000Hz, actual 148500000HZ div = 0) > [ 4835.305419] dwmmc_rockchip fe320000.mmc: Successfully tuned phase to 213 > [ 4836.346928] mmcblk1: p1 p2 Swapping with a "highspeed" (non-UHS) card also seems to work > [ 5733.702083] mmc1: card 0001 removed > [ 5738.858439] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) > [ 5739.378487] mmc_host mmc1: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0) > [ 5739.378627] mmc1: new high speed SD card at address 21bb > [ 5739.380491] mmcblk1: mmc1:21bb APPSD 480 MiB > [ 5739.382795] debugfs: Directory 'mmcblk1' with parent 'block' already present! > [ 5739.385096] mmcblk1: p1 > [ 5774.386536] FAT-fs (mmcblk1p1): utf8 is not a recommended IO charset for FAT filesystems, filesystem will be case sensitive! > [ 5795.486365] mmc1: card 21bb removed > [ 5801.302688] mmc_host mmc1: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0) > [ 5801.447128] mmc_host mmc1: Bus speed (slot 0) = 148500000Hz (slot req 150000000Hz, actual 148500000HZ div = 0) > [ 5801.880374] dwmmc_rockchip fe320000.mmc: Successfully tuned phase to 211 > [ 5801.880440] mmc1: new ultra high speed SDR104 SDHC card at address 0001 > [ 5801.882253] mmcblk1: mmc1:0001 ASTC 14.6 GiB > [ 5801.884145] debugfs: Directory 'mmcblk1' with parent 'block' already present! > [ 5801.886558] mmcblk1: p1 p2 > Some debug output: cat /sys/kernel/debug/mmc1/ios UHC > clock: 150000000 Hz > actual clock: 148500000 Hz > vdd: 18 (3.0 ~ 3.1 V) > bus mode: 2 (push-pull) > chip select: 0 (don't care) > power mode: 2 (on) > bus width: 2 (4 bits) > timing spec: 6 (sd uhs SDR104) > signal voltage: 1 (1.80 V) > driver type: 0 (driver type B) non-UHC > cat /sys/kernel/debug/mmc1/ios > clock: 50000000 Hz > vdd: 18 (3.0 ~ 3.1 V) > bus mode: 2 (push-pull) > chip select: 0 (don't care) > power mode: 2 (on) > bus width: 2 (4 bits) > timing spec: 2 (sd high-speed) > signal voltage: 0 (3.30 V) > driver type: 0 (driver type B) > How do I make sure I specifically send the soft-reset command? I'm happy to help but I'm really a novice here. Best, Christian
