On Thu, 30 Jun 2022 at 11:09, Eugen Hristev <eugen.hristev@xxxxxxxxxxxxx> wrote:
>
> In set_uhs_signaling, the DDR bit is being set by fully writing the MC1R
> register.
> This can lead to accidental erase of certain bits in this register.
> Avoid this by doing a read-modify-write operation.
>
> Fixes: d0918764c17b ("mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection")
> Signed-off-by: Eugen Hristev <eugen.hristev@xxxxxxxxxxxxx>
> Tested-by: Karl Olsen <karl@xxxxxxxxxxxxxxxxx>
Applied for next, thanks!
Kind regards
Uffe
> ---
> drivers/mmc/host/sdhci-of-at91.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
> index 10fb4cb2c731..cd0134580a90 100644
> --- a/drivers/mmc/host/sdhci-of-at91.c
> +++ b/drivers/mmc/host/sdhci-of-at91.c
> @@ -100,8 +100,13 @@ static void sdhci_at91_set_clock(struct sdhci_host *host, unsigned int clock)
> static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host,
> unsigned int timing)
> {
> - if (timing == MMC_TIMING_MMC_DDR52)
> - sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
> + u8 mc1r;
> +
> + if (timing == MMC_TIMING_MMC_DDR52) {
> + mc1r = sdhci_readb(host, SDMMC_MC1R);
> + mc1r |= SDMMC_MC1R_DDR;
> + sdhci_writeb(host, mc1r, SDMMC_MC1R);
> + }
> sdhci_set_uhs_signaling(host, timing);
> }
>
> --
> 2.25.1
>
