Hi Rob, On Tue, Jun 14, 2022 at 2:30 PM Rob Herring <robh@xxxxxxxxxx> wrote: > > On Mon, Jun 13, 2022 at 12:56:49PM -0700, Brad Larson wrote: > > From: Brad Larson <blarson@xxxxxxx> > > > > Add support for the AMD Pensando Elba SoC System Resource chip > > using the SPI interface. The Elba SR is a Multi-function Device > > supporting device register access using CS0, smbus interface for > > FRU and board peripherals using CS1, dual Lattice I2C masters for > > transceiver management using CS2, and CS3 for flash access. > > > > Signed-off-by: Brad Larson <blarson@xxxxxxx> > > --- > > .../bindings/mfd/amd,pensando-elbasr.yaml | 93 +++++++++++++++++++ > > 1 file changed, 93 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml > > > > diff --git a/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml > > new file mode 100644 > > index 000000000000..13356800b1cf > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/mfd/amd,pensando-elbasr.yaml > > @@ -0,0 +1,93 @@ > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/mfd/amd,pensando-elbasr.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: AMD Pensando Elba SoC Resource Controller bindings > ... > > +patternProperties: > > + '^reset-controller@[a-f0-9]+$': > > + $ref: ../reset/amd,pensando-elbasr-reset.yaml > > /schemas/reset/... Changed it to $ref: /schemas/reset/amd,pensando-elbasr-reset.yaml > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/reset/amd,pensando-elba-reset.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + > > + spi0 { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + num-cs = <4>; > > + > > + spi@0 { > > + compatible = "amd,pensando-elbasr", "simple-mfd"; > > + reg = <0>; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + spi-max-frequency = <12000000>; > > + > > + rstc: reset-controller@0 { > > Only one child does not make a MFD... Looking over the approaches for other SoCs with an external required controller (cpld, fpga) this appeared to be an acceptable choice. This device is accessed by several different utilities/programs via /dev/pensr0.x, CS0 registers for a variety of control/status, CS1 designware i2c master/slave, CS2 lattice dual i2c masters, and CS3 for flash. > > + compatible = "amd,pensando-elbasr-reset"; > > + reg = <0>; > > + #reset-cells = <1>; > > + }; > > + }; > > + > > + spi@1 { > > + compatible = "amd,pensando-elbasr", "simple-mfd"; > > + reg = <1>; > > + spi-max-frequency = <12000000>; > > 'simple-mfd' implies there are child nodes, but you have none. Is this > complete? This function is a designware i2c master/slave for board peripheral access. Removed simple-mfd. > > + }; > > + > > + spi@2 { > > + compatible = "amd,pensando-elbasr", "simple-mfd"; > > + reg = <2>; > > + spi-max-frequency = <12000000>; > > + interrupt-parent = <&porta>; > > + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; > > This one has interrupt but the others don't? Yes, this function is a Lattice dual I2C master for transceiver management. The spi to i2c driver is not included in this patch set for essential Elba SoC support. Removed simple-mfd. Regards, Brad
